asic - 技术专题

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Here are 959 public repositories matching this topic...

skywater-pdk

google / skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

magic asic eda pdk asic-library openroad openram skywater

Updated Jul 21, 2026
Python

openhwfoundation / cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

asic cpu fpga risc-v systemverilog-hdl rv64gc ariane

Updated Oct 4, 2026
Assembly

neorv32

stnolting / neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller asic cpu fpga processor vhdl verilog soc risc-v soft-core

Updated Oct 4, 2026
VHDL

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Mar 25, 2026
Python

serv

olofk / serv

SERV - The SErial RISC-V CPU

asic fpga verilog risc-v

Updated Aug 25, 2026
Verilog

ultraembedded / riscv

RISC-V CPU Core (RV32IM)

asic cpu fpga verification verilog pipeline-processor risc-v rv32i verilator riscv-linux rv32im

Updated Sep 18, 2021
Verilog

pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

Updated Sep 24, 2026
SystemVerilog

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

Updated Oct 4, 2026
Haskell

ucb-bar / gemmini

Berkeley's Spatial Array Generator

asic accelerator dnn

Updated Oct 4, 2026
Scala

ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Sep 18, 2021
Verilog

siliconcompiler / siliconcompiler

Modular hardware build system

asic fpga hls vhdl eda rtl verilog make synthesis cmos

Updated Oct 5, 2026
Python

splinedrive / kianRiscV

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

linux asic cpu fpga x11 riscv verilog xv6 systemverilog mmu soc system-on-chip rv32ima chipdesign tinytapeout sv32

Updated May 29, 2026
Verilog

esig / dss

Digital Signature Service : creation, extension and validation of advanced electronic signatures

java asic validation signature xades cades pades esignature jades

Updated Aug 28, 2026
Java

ultraembedded / cores

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

riscvarchive / riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

asic fpga risc-v socs open-isa

Updated Mar 26, 2021

VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

unit-testing asic fpga vhdl verification testbench verilog-hdl systemverilog-hdl universal-verification-methodology

Updated Oct 3, 2026
VHDL

VLSI-EDA / PoC

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

python asic fpga simulation vhdl verification xilinx synthesis regression-testing altera hardware-designs lattice hardware-libraries poc-library vlsi testbenches hardware-modules osvvm uvvm vunit

Updated Jul 30, 2025
VHDL

librelane / librelane

ASIC implementation flow infrastructure, successor to OpenLane

asic eda digital-design electronic-design-automation asic-design openlane chip-design librelane

Updated Sep 28, 2026
Python

zssloth / Embedded-Neural-Network

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

compression asic fpga deep-learning neural-network

Updated Feb 3, 2024

pulp-platform / ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

asic cpu vector riscv ara rvv rv64gcv

Updated Sep 22, 2026
C

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