rv32i 开源项目推荐（349 个）

ultraembedded /riscv

RISC—V CPU 核心 （ RV32IM ）

sysprog21 /shecc

A self-hosting and educational C optimizing compiler

ultraembedded /biriscv

32-bit Superscalar RISC-V CPU

syntacore /scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

WangXuan95 /USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

MPSU /APS

Laboratory course on RISC-V Processor Development

rafaelcalcada /rvx

RISC-V 微控制器 IP 核心，用于嵌入式、FPGA 和 ASIC 应用

tscheipel /HaDes-V

HaDes-V 是用于学习微控制器设计的开放教育资源。它引导你使用 SystemVerilog 和 FPGA 工具创建流水线式 32 位 RISC-V 处理器。该资源由 TU Graz 的 EAS Group 开发，将硬件/软件协同设计中的动手练习与在 Basys3 FPGA 板上的实际实现相结合。

chenyuliu577-cyber /jyd-rv32i-fpga-core

Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.

AngeloJacobo /RISC-V

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Gaok1 /Raven-RiscV

RISC-V simulator and IDE for learning assembly — RV32IMF, step-by-step debugger,cache , pipeline, multi-core simulator

RISC-KC /basic_rv32s

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

stnolting /riscv-gcc-prebuilt

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

sysprog21 /ca2025-mycpu

RISC-V CPU Labs in Chisel

martinKindall /risc-v-single-cycle

A Single Cycle Risc-V 32 bit CPU

aignacio /nox

RISC-V Nox core

maikmerten /spu32

Small Processing Unit 32: A compact RV32I CPU written in Verilog

FelipeFFerreira /ITA-CORES

RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

calint /tang-nano-9k--riscv--cache-psram

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

saursin /riscv-atom

An open-source 32-bit RISC-V soft-core processor