chip-design 开源项目推荐（178 个）

librelane /librelane

ASIC 实现流程基础设施，OpenLane 的继任者

keplertech /kepler-formal

Digital Design Equivalence Checking

mirseo /JSilicon

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

TinyTapeout /ttihp-verilog-template

Submission template for Tiny Tapeout IHP shuttles - Verilog HDL Projects

eskiyerli /revolution-eda

Revolution EDA repository, an integrated schematic to GDS design environment for custom integrated circuits

patrickschulz /openPCells

Parametric layout generator for digital, analog and mixed-signal integrated circuits

bjwanneng /veriflow-cc

VeriFlow-CC：一个基于Claude代码的RTL设计流水线。利用有状态、零依赖的LLM编排技能，自动化Chip-on-Chat从架构到综合（iVerilog/Yosys）。具备子代理嵌套功能，用于代码生成和行为驱动的验证。

Zaneham /takahe

open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists

gdsfactory /quantum-rf-pdk

Sample PDK for Superconducting RF Quantum Circuits

The-OpenROAD-Project /OpenROAD-MCP

Model Context Protocol (MCP) server for OpenROAD

mabrains /sky130_klayout_pdk

Skywater 130nm Klayout Device Generators PDK

arhamhashmi01 /rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

popovych-labs /open-npu

Open NPU is an open-source project dedicated to creating a flexible, extensible, and high-performance neural processing unit (NPU) architecture. Open NPU aims to democratize access to cutting-edge neural processing technology for machine learning and AI applications.

shsridhar-beep /svgap

Evidence profiles for AI-generated RTL that expose what functional benchmarks miss. Seeking collaborators, design partners, and validation

phamcuong21478 /rtl-skills

Claude Code skills & agents that automate a full RTL/Verilog design flow - architecture, RTL coding, lint, simulation, self-checking testbenches, regression, debug, Vivado synthesis, and docs - driven from a one-page IP spec.

du-du-wang /silicon-canvas

Help AI create clear, beautiful, and consistent chip visuals—from architecture diagrams and dataflows to polished product renders.

Noamv7 /Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

该项目专注于数字逻辑电路的设计和验证，特别是针对使用Verilog、SystemVerilog和SVA的芯片设计。主要目标包括设计符合行业标准的模块，如APB（高级外设总线）、内存系统和systolic矩阵乘法。

ojasvi-shah /Advanced-Physical-Design-Using-OpenLANE--Ojasvi-Shah

Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah

AlpharomeroJL /reticle

Browser-native, GPU-accelerated editor for very large hierarchical 2D IC-layout scenes, written in Rust (native and WebAssembly).

edacommons /rawast

面向 EDA 文件格式的通用双向语法驱动引擎。同一套语法驱动 GDSII、LEF、DEF、Tcl 的解析与保存。