开源工艺设计套件,可与SkyWater Technology Foundry的130纳米节点配合使用。
openram 开源项目推荐(13 个)
openram 话题在 GitHub 上没有填写简介,这里按 Star 数汇总最相关的热门仓库。
热门项目 全部 13
GitHub 共 13 个仓库,已全部展示OpenLane是一个自动RTL到GDS II流程,基于多个组件,包括OpenROAD、Yosys、Magic、Netgen以及用于设计探索和优化的自定义方法学脚本。
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
Open-source MBIST, BIRA and BISR generator for OpenRAM memories, taken through RTL-to-GDS on sky130 with LibreLane
Production-quality RV32IM SoC built on PicoRV32 — FreeRTOS port, UVM verification, JTAG debug, and full ASIC tapeout flow on SkyWater sky130.
A robust, automated SRAM compiler workflow based on OpenRAM. Features fixes for modern Python/Numpy environments, automated multi-bank generation, and Synopsys (DB/NDM) post-processing.
SKY130 SRAM generation, real-area closure, multi-tool output organization, and delivery packaging for 1RW and 1R1W memories.
HeteroCore component: SRAM hierarchy model and OpenRAM config generator
AI-Assisted 4KB SRAM Design using OpenRAM and SKY130 PDK
5-stage pipelined RISC-V (RV32I subset) processor in SystemVerilog that runs compiled C through variable-latency memories over an OBI-style request/ready protocol. Full ASIC flow: Synopsys DC synthesis at 641 MHz and Cadence Innovus place & route on NanGate 45 nm, plus OpenRAM SSRAM integration.
关于这个话题
- 清单取自 GitHub 话题页并按 Star 数排序,每次展示前 13 个项目;原始页面见 https://github.com/topics/openram。
- 该话题在 GitHub 上共有 13 个仓库, 本站收录的是其中最热门的 13 个,不是全量列表。
- Star / Fork 每日自动刷新一次,实时数据以 GitHub 为准。
- 当前 13 个项目累计 6457 Star,覆盖 6 种主要语言,数据更新于 2026-11-07。
- 中文介绍来自 GitHub 官方话题说明(github/explore)的机器翻译,可点「查看原文」对照;译文缺失时会先展示原文。