axi 开源项目推荐（215 个）

pulp-platform /axi

用于高性能片上通信的 AXI SystemVerilog 可综合 IP 模块与验证基础设施

taichi-ishitani /tvip-axi

AMBA AXI VIP

rggen /rggen

Code generation tool for control and status registers

ZipCPU /sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

pulp-platform /FlooNoC

A Fast, Low-Overhead On-chip Network

SystemRDL /PeakRDL

Control and status register code generator toolchain

hdl-modules /hdl-modules

一系列可重复使用、高质量、经过同行评审的ADL构建块。

taichi-ishitani /tnoc

Network on Chip Implementation written in SytemVerilog

lucky-wfw /ARM_AMBA_Design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

lcapossio /fpgacapZero

fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI

hdl-registers /hdl-registers

An open-source HDL register code generator fast enough to run in real time.

pulp-platform /axi_mem_if

Simple single-port AXI memory interface

shiftynick /jev-axi

Agent-ergonomic CLI for TypeSafe's Jev: fast calibrated judgments (pick, rate, check, rank, triage, guard) from the shell

esynr3z /axi_vip_demo

Xilinx AXI VIP example of use

qingxuanxx /sv_uvm_axi_notes

数字IC验证学习笔记：SV/UVM/AMBA总线（AXI/APB/AHB/AXI-Lite/AXI-Stream）+ 数字IC验证校招面经

atfox272 /AXI4-Interconnect

RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.

QuillAtNova73812 /eft-dma-radar-rpocket

PCIe DMA-based external game state reader. Hardware DMA capture, memory layout discovery, no in-process injection. C#

RSPwFPGAs /opae-xilinx

OPAE porting to Xilinx FPGA devices.

d953i /Custom_Part_Data_Files

Xilinx PCIe to MIG DDR4 example designs and custom part data files

SACHINUR17 /VLSI-Design-Verification-Projects

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects