pipeline-processor 开源项目推荐（100 个）

ultraembedded /riscv

RISC—V CPU 核心 （ RV32IM ）

pypyr /pypyr

用于自动化管道的pypyr任务运行者脚本和API。通过将命令、不同语言的不同脚本和应用程序组合到一个管道流程中来自动化任何事情。

gchq /stroom

Stroom is a highly scalable data storage, processing and analysis platform.

KASIRGA-KIZIL /tekno-kizil

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

Armatiek /xslweb

Web application framework for XSLT and XQuery developers

wwoods /job_stream

An MPI-based C++ or Python library for easy distributed pipeline processing

phillbush /legv8

LEGv8 CPU implementation and some tools like a LEGv8 assembler

arhamhashmi01 /rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

saantiaguilera /go-pipeline

Build, execute and represent pipelines (aka workflows / templates) in Go

sdasgup3 /parallel-processor-design

Super scalar Processor design

brunocampos01 /organizacao-e-arquitetura-de-computadores

Repositório para as aulas, exercícios e resumos da matéria: organização e arquitetura de computadores (INE5607).

djzenma /RV32IC-CPU

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

cjrh /excitertools

itertools (and more-itertools) in the form of function call chaining (fluent interface)

aman-nidhi /CSF342-Computer-Architecture

MIPS32 Assembly, Sorting Example in MIPS32 Assembly, CS-F342-Computer-Architecture-Lab

pypyr /pypyr-example

pypyr 流水线运行器 CLI 示例

pouriya /pipeline

Have pipeline in Erlang

TheLeopardsH /RISC-V-5-stage-pipelined-in-verilog

RISC-V-5 stage pipelined in verilog

DTV96Calibre /pipelined-mips

A Verilog implementation of a pipelined MIPS processor

strongwong /bittyCore_RISC-V

This is a bitty CPU core of risc-v architecture, which is currently under development.

Panda-Cores /PandaZero

A pipelined, in-order implementation of the RV32I ISA