soft-core 开源项目推荐（36 个）

stnolting /neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

ZipCPU /zipcpu

一个体积小、重量轻的RJ中央处理器软核

WangXuan95 /FPGA-DDR-SDRAM

An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

stnolting /neo430

一个极小的兼容 msp430、可定制的类微控制器软核处理器系统，使用平台无关的 VHDL 编写。

RISC-KC /basic_rv32s

教学用 RISC-V 处理器设计框架：从单周期到 5 级流水线，包含 FPGA 验证和完整学习指南！一份 RISC-V CPU 设计指南。

popovicu /mrav-cpu

A fully automated, custom CPU and software stack for tiny embedded systems

sy2002 /QNICE-FPGA

QNICE-FPGA 是一个用于娱乐编程的 16 位计算机系统，以可移植 VHDL 构建为完整的片上系统。

lxp32 /lxp32-cpu

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

wyvernSemi /riscV

Open source ISS and logic RISC-V 32 bit project

saursin /riscv-atom

An open-source 32-bit RISC-V soft-core processor

matt-alencar /fpga-uart-tx-rx

Basic UART TX/RX module for FPGA

Kingfish404 /raptor-chip

Superscalar OoO RISC-V CPU, marchid: 50 (0x32), RVA22S64/RVI20U32.

mrisc32 /mrisc32-a1

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

Peymanc1 /RV32IM-from-scratch

A RISC-V RV32IM CPU and SoC built from scratch in SystemVerilog — single-cycle → 5-stage pipeline, caches, AXI4 + DDR, HDMI — running DOOM on a Zybo Z7-20. Spike-verified, Verilator-simulated.

wyvernSemi /mico32

LatticeMico32 instruction set simulator project

true-grue /uzh

Uzh compiler

semahawk /icarium

Trying to implement a soft core SoC

ArbnorSh /RV-PipelineCore

RISC-V processor in compliance with RV32IMZicsr

Sarkar22 /hades-v-plus

Extended RISC-V soft core targeting the Basys3 FPGA: RV32IM + Zba + Zicsr/Zifencei/Zicntr on a 5-stage in-order pipeline with a branch predictor. Runs FreeRTOS with an interactive shell in Verilator simulation; formally verified multiply/divide unit. Built on TU Graz's HaDes-V.

AndrejChoo /AVR_like_core_on_verilog

Soft core with support for the AVR8 instructions on verilog