caravel 开源项目推荐（24 个）

The-OpenROAD-Project /OpenLane

OpenLane是一个自动RTL到GDS II流程，基于多个组件，包括OpenROAD、Yosys、Magic、Netgen以及用于设计探索和优化的自定义方法学脚本。

efabless /caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

efabless /caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

0x01be /rudder

Learn, share and collaborate on ASIC design using open tools and technologies

efabless /clear_old

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.

neevany /caravel-on-heroku

One-button Heroku deploy for the Caravel data exploration platform.

kbeckmann /caravel-pll-calculator

PLL configuration generator for the Caravel management core

FPGA-Research /FABulous_board

A PCB created for FABulous FPGAs, based on the caravel board.

CDragon123-code /caravel-sha256-accelerator

SHA-256 accelerator on Caravel SoC (SkyWater 130nm) - open-source RTL-to-GDSII signoff flow

efabless /caravel_ibex

An example project that utilizes caravel user space for an ibex based SoC

bazx-bit /caravel-direct-rf

Cognitive Direct-RF Sampling Transceiver: Massively pipelined SDR DSP baseband engine hardened on SkyWater 130nm for Efabless Caravel OpenMPW tapeout. 100-phase SystemVerilog RTL, OpenLane ASIC signoff, and 100% regression verified.

Bhavuk-HDL /custom-asic

Eight different verilog projects are combined to creat a big custom asic project.

truong92cdv /aes

Implementing an AES ecnryption IP Core with Caravel Platform

Mummanajagadeesh /fir-accel-caravel-soc

Mixed-signal FIR accelerator SoC on Caravel/Sky130A — CIC decimator, 8-tap programmable FIR filter, PWM DAC, Wishbone CSR

DivyamGoyal-github /RISC_V-SoC-Tapeout-Program_VSD_Caravel_IITGN_Phase2

This repository contains documentation and relevant materials for the RISC-V SoC Tapeout Program, a collaborative initiative between IIT Gandhinagar, VLSI System Design (VSD), and other prominent organizations in the field of semiconductor design.

hemachandhran /Open-Source-ASIC-Design-RTL-to-GDSII

Hands-on open-source ASIC design portfolio documenting the complete RTL-to-GDSII flow, SoC verification, and gate-level simulation using OpenLane, OpenROAD, SKY130, Caravel, and VSDSquadron.

ShekharShwetank /RISC-V_Reference_SoC_Tapeout_Program_Phase_2

RISC-V Reference SoC Design and Tapeout Program Phase 2 personal documentation

Pa1mantri /VSDSquadron_RTL_GDSII

Verified a physically implemented 32-bit Wishbone slave wrapper using mixed-level simulation, successfully integrating the Gate-Level Netlist within the full Caravel RTL SoC environment to ensure system-level compatibility.

truong92cdv /caravel_aes_accelerator

Implementing an AES ecnryption IP Core with Caravel Platform

Mysha-Fathima /VSD-SQUADRON-RTL2GDSII

RTL-to-GDSII flow implementation using the VSDsquadron development board. Built during a 6-week intensive SoC design and simulation program with VSD Platform.