axi4 开源项目推荐（123 个）

pulp-platform /axi

用于高性能片上通信的 AXI SystemVerilog 可综合 IP 模块与验证基础设施

chipsalliance /Cores-VeeR-EH1

VeeR EH1 核心

taichi-ishitani /tvip-axi

AMBA AXI VIP

Hanley-Yao /Zynq7010_eink_controller

这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS

chipsalliance /Cores-VeeR-EL2

VeeR EL2 Core

dpretet /axi-crossbar

Parametric AXI4 crossbar in SystemVerilog

WangXuan95 /FPGA-DDR-SDRAM

An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

taichi-ishitani /tnoc

Network on Chip Implementation written in SytemVerilog

aignacio /ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

OSVVM /AXI4

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

loykylewong /FPGA-Application-Development-and-Simulation

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。 Source Code of the book FPGA Application Development and Simulation(CHS).

ultraembedded /core_sdram_axi4

SDRAM controller with AXI4 interface

mmxsrup /axi4-interface

AX 4和AX 4-Lite接口定义

ultraembedded /core_ft60x_axi

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

ultraembedded /core_dvi_framebuffer

Minimal DVI / HDMI Framebuffer

ultraembedded /core_dbg_bridge

UART -> AXI Bridge

airhdl /spi-to-axi-bridge

SPI到AX 4-Lite桥，可轻松实现airhdl寄存器组与任何微控制器的接口。

ultraembedded /core_spiflash

SPI-Flash XIP Interface (Verilog)

atfox272 /AXI4-Interconnect

RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.

ic-lab-duth /NoCpad

HLS for Networks-on-Chip