sdram 开源项目推荐（66 个）

ultraembedded /cores

各种HDL（Verilog）IP核

1a2m3 /SPD-Reader-Writer

SPD 读写器，具备软件写保护功能，支持 Arduino 和 SMBus

nullobject /sdram-fpga

A FPGA core for a simple SDRAM controller.

hdl-util /sdram-controller

通用FPGA SDRAM控制器，最初为AS4C4M16SA设计

jasonsbeer /Amiga-N2630

A re-imagining of the Amiga A2630 processor card.

maojinxiang /FPGA-ANLU-National-First-Prize

2025年全国大学生嵌入式芯片与系统设计竞赛（FPGA赛道）国家一等奖作品，安路二赛道

yigitbektasgursoy /SDRAM_Verilog

Verilog HDL implementation of SDRAM controller and SDRAM model

ghent360 /riscvOnColorlight-5A-75B

RISC-V soft core running on Colorlight 5B-74B.

AngeloJacobo /FPGA_SDRAM_Controller

SDRAM controller optimized to a memory bandwidth of 316MB/s

iliasam /stm32f429_vga_examples

Code examples of using STM32F429 for generating VGA image.

machdyne /kuchen

Kuchen Computer

oscc-ip /sdram

An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

qubeck78 /tangerineA7_200

RiscV based SOC for Qmtech Artix A7-200 board. Includes nekoRv: RISC-V 32 IM Zicsr core. And yes, it runs DOOM :)

andrempmattos /harsh-payload

Harsh Environment CubeSat Payload designed to evaluate three different manufacturing nodes SDR SDRAM technologies under space radiation conditions. It was developed for the FloripaSat-2 CubeSat mission.

perehinik /SDRAM_Controller

Verilog SDR SDRAM controller for FPGA Xilinx and Lattice

har-in-air /SIPEED_TANG_PRIMER

Projects using the Sipeed Tang Primer FPGA development board

Arkowski24 /sdram-controller

Simple SDRAM Controller for DE10-Lite.

MinatsuT /CYC1000_SDRAM

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

agg23 /sdram-controller

A HDL SDRAM controller designed for retro hardware and FPGAs

cw1997 /SDRAM-Controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol