genus 开源项目推荐（27 个）

ramiomer94 /VLSI-design-projects

本仓库包含约克大学 EECS 4612：数字 VLSI 设计课程中完成的所有主要项目。这些项目展示了完整的 ASIC 设计流程——从 RTL 设计到 GDSII 版图——并使用 Cadence Genus、Innovus 和 Virtuoso 等行业级工具。

yangyuqian /genus

A general code generation tools for Go applications

SanderGi /Genus

State of the art algorithms for computing the genus of a graph and visualizing the corresponding embedding. Python bindings, C code, and an interactive web app.

Kev1nLevin /matmul-engine

Parameterized N×N output-stationary systolic array accelerator for INT8 neural network inference. Full RTL-to-GDS flow on ASAP7 7nm using Cadence Genus + Innovus. 667 MHz, 42.7 GOPS peak throughput, 0.33 mW/GOP. SystemVerilog RTL, synthesis, place-and-route and self-checking testbench included.

NikolaosGian /VLSI-ASIC-IC

An application using Cadence IC Package

zenitheesc /Genus

Genus is a generic hardware platform aimed at instrumentation in aerospace projects.

jefferyphein /ternary-birch

A library for computing Hecke matrices, eigenvectors, and eigenvalues for positive definite rational ternary quadratic forms.

tylerhuyser /CanYouEatItFungusIdentificationApp

CAN YOU EAT IT is a web application that allows users to identify fungi by location & season.

wILLIEWILLYWILLIe /MNIST-NPU-ASIC

A complete ASIC design flow for a MNIST NPU. Features a quantized hardware-friendly architecture, SystemVerilog RTL implementation, and a verified backend-ready flow for logic synthesis and GDSII generation.

anupamsarashwat1-cloud /smvdu-titan-x

A high-performance, production-grade 64-bit RISC-V Multicore SoC ecosystem and industry-standard Cadence ASIC CAD flow (Genus/Innovus). Fully integrated 5-hart coherent core complex, TileLink interconnect, custom RoCC ML Systolic Array, PCIe, USB, HDMI, and silicon-proven IP blocks.

bbzaffari /FIFO-2-Very-Large-Scale-Integration

VHDL implementation of an "asynchronous" FIFO with 64 positions of 8-bit words. Features dual clock domains (wr_clk, rd_clk), asynchronous reset, status signals (empty, full, almost empty/full, error), testbench, synthesis scripts, and timing/power/area reports.

Shubham-G04 /In-Memory-Computing-Applied-on-an-8x8-6T-SRAM-Array

Comparative VLSI design, layout, and simulation of an 8×8 6T SRAM cell array with embedded In-Memory Computing (IMC) capabilities across 180 nm, 90 nm, and 45 nm CMOS technology libraries in Cadence Virtuoso and cross checking functionality using VerilogHDL

celuk /cadence-flow

Standalone Cadence Genus & Innovus Flow

fromabhinavkr /Design-and-Implementation-of-High-Performance-and-Low-Power-RISCV-Processor

This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC

rarredon /genus

Python program to compute genera of surfaces into which simple 4-valent rigid vertex graphs can be embedded

GHOSTALERT /harris-corner-asic

Streaming Harris corner detector ASIC in SystemVerilog, RTL to GDSII with Cadence Genus/Conformal/Tempus/Innovus (90 nm, 250 MHz)

zenitheesc /Genus-OBC

On-Board Computer for aerospace systems

zenitheesc /Genus-CDH

Communications and Data Handling for aerospace systems

el3ctrician /el3ctrician.github.io

public personal website

zenitheesc /Genus-IAC

Image Acquisition Component for aerospace systems