logic-synthesis 开源项目推荐（107 个）

lsils /lstools-showcase

Showcase examples for EPFL logic synthesis libraries

NYU-MLDA /OpenABC

OpenABC-D 是一个大规模标记数据集，通过合成开源硬件 IP 生成。该数据集可用于芯片设计中的各种图级预测问题。

scale-lab /DRiLLS

DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)

lnis-uofu /LSOracle

IDEA project source files

msoeken /cirkit

A circuit toolkit

clin99 /awesome-eda

该项目在 GitHub 上没有填写描述

cda-tum /fiction

An open-source design automation framework for Field-coupled Nanotechnologies

nbulsi /also

A logic synthesis tool

marcelwa /aigverse

A Python library for working with logic networks, synthesis, and optimization.

bojackchen /digital-flow

这是一份关于标准数字设计流程的教程

workcraft /workcraft

Toolset to capture, simulate, synthesize and verify graph models

scale-lab /OpenPhySyn

EDA physical synthesis optimization kit

lsils /kitty

C++ truth table library

The-OpenROAD-Project /yosys

Logic synthesis and ABC based optimization

ieee-ceda-datc /RDF-2019

DATC RDF

panhomyoung /phyLS

A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""

hriener /lorina

C++ parsing library for simple formats used in logic synthesis and formal verification

cornell-zhang /HOGA

Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits

scale-lab /BLASYS

An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization

scale-lab /DRUM

The Verilog source code for DRUM approximate multiplier.