asap7 话题在 GitHub 上没有填写简介，这里按 Star 数汇总最相关的热门仓库。
Parameterized N×N output-stationary systolic array accelerator for INT8 neural network inference. Full RTL-to-GDS flow on ASAP7 7nm using Cadence Genus + Innovus. 667 MHz, 42.7 GOPS peak throughput, 0.33 mW/GOP. SystemVerilog RTL, synthesis, place-and-route and self-checking testbench included.
Open research toward model-specific mask-ROM LLM inference silicon: analytical studies, an ABI 3.0 compiler/runtime and cycle model, synthesizable RTL, and open-PDK physical evidence — gated against itself by a 19-rung board that is deliberately mostly red.
Autonomous RISC-V CPU replication of 'Design Conductor' (arxiv:2603.08716) — 1.525 GHz, 2,358 µm² cell area, CoreMark 9,541, ASAP7 SLVT, open-source EDA only. Personal side project.
Open-source silicon: 10 hardware accelerator projects from SystemVerilog RTL to 7nm GDSII. CPUs (RISC-V + RVV), ML accelerators (conv, attention, sparse matmul, FP8/BF16), crypto (SHA-256/3, ML-KEM), graphics (ray-trace), and FPU library — all with bit-exact pymodel verification and cocotb tests.
Benchmarking framework for ISPD'23 contest and TCHES'25 paper.
𓁰 PtahCore — open-source FP8 tensor accelerator, RTL→GDSII on open 7nm ASAP7, 100% open toolchain
Transistor-level design and characterization in ASAP7 7nm FinFET: a dual-Vt domino AND8 (11% leakage reduction) and 6T vs 8T SRAM bitcells across read, write, and hold. Includes a measurement-setup discrepancy found in the original decks.
Mini Stereo Digital Audio Processor taken RTL-to-GDSII on ASAP7 7 nm: stereo Verilog RTL, SRAM integration, Genus synthesis, Innovus implementation, and verification docs.
CHERIoT capability-enforcing DMA engine in SystemVerilog. Includes ASAP7 7nm PPA with Genus/Innovus.
7 nm FinFET standard-cell library, registered 3-bit arithmetic unit, synthesis artifacts, and physical-design reports.
Open Source SRAM compiler for the ASAP7 7nm process, with its own verification stack
GCN inference accelerator taken from RTL to routed layout on the ASAP7 7 nm PDK: OpenROAD timing closure at 1,450 ps, and an OpenSTA re-time that found untimed latch paths.
OpenTitan Prim Asap7 IP block
Exploring better per-design recipes for open-source logic synthesis with machine learning and surrogate-guided search