eda-tools 开源项目推荐（48 个）

arm-education /VLSI-Fundamentals-Education-Kit

利用工业EDA工具通过实用微处理器设计教授VLSI基础知识的教育工具包（教育用）

ref42 /seex

批量导出立创商城元件为Altium Designer（AD）、KiCad、Cadence（OrCAD Capture / Allegro）可用的格式。Batch export LCSC components from the command line into formats supported by Altium Designer (AD) , KiCad and Cadence（OrCAD Capture / Allegro.

ref42 /npnp

批量导出立创商城元件为Altium Designer（AD）、KiCad、Cadence（OrCAD Capture / Allegro）可用的格式。Batch export LCSC components from the command line into formats supported by Altium Designer (AD) , KiCad and Cadence（OrCAD Capture / Allegro.

fayizferosh /yosys-tcl-ui-report

5 Day TCL begginer to advanced training workshop by VSD

ramiomer94 /VLSI-design-projects

本仓库包含约克大学 EECS 4612：数字 VLSI 设计课程中完成的所有主要项目。这些项目展示了完整的 ASIC 设计流程——从 RTL 设计到 GDSII 版图——并使用 Cadence Genus、Innovus 和 Virtuoso 等行业级工具。

algosup /2024-2025-project-4-web-fpga-team-3

A web-based tool for parsing and visualizing FPGA. It provides an interactive graph representation of signal propagation, helping engineers and students analyze delays, interconnections, and logic components inside an FPGA.

AkshatIsWired /lanex

Browser cockpit & IDE for the LibreLane RTL-to-GDS chip flow — run, verify, and explore silicon flows without living in a terminal.

ADolbyB /vlsi-spice-pcbs

A collection of Schematics, PCBs and VLSI work on various platforms

Samizo-AITL /Edusemi-v4x

An integrated educational framework covering semiconductor physics, circuit design, fabrication processes, and testing — from fundamentals to advanced practical applications. （物性・回路・プロセス・設計・テストを貫く一貫教育体系。基礎から応用・実践までを体系的に整理）

edacommons /parameda

Param + EDA — a hierarchical configuration system for EDA tooling: config-folder tree with parent/child scoping, lazy variable substitution, and JSON-backed load/save.

vyges-tools /sta-si

Static timing analysis with signal integrity — WNS/TNS sign-off gate, SI/crosstalk + statistical OCV.

vyges-tools /drc

Design-rule check: a GDS layout + a rule deck in, geometry violations out.

meshlinklabel /Proteus-Design-Suite-Professional-Build

Proteus Design Suite Professional — electronics simulation with SPICE, PCB layout and microcontroller co-simulation.

bdivya-9125 /Comparative-Study-of-16bit-Adder-Architectures

Design and simulation of 16-bit Ripple Carry and Weinberger Adders using Cadence Virtuoso. Includes full adder modeling, schematic creation, waveform analysis, and detailed delay-power comparison.

agneya-na /OpenLEC

Open-source, Python-native EDA toolchain for Low-Power Logic Equivalence Checking (LEC) and IEEE 1801 UPF verification - SAT-based (Yosys) equivalence flow + agentic multi-agent optimization. MIT licensed.

kaiwenyu147369 /verilog-mcp-server

AI-powered Verilog/SystemVerilog MCP Server for Claude Code: generate testbenches, lint RTL code, and scaffold UVM verification environments

Onely7 /local_data_studio

A local data studio for JSONL/JSON/CSV/TSV/Parquet: scalable previews, image inspection, DuckDB SQL, EDA, and Embedding Atlas.

mittalsaks /eSimToolManager

OS-independent CLI tool that checks dependencies for eSim's integrated EDA tools (Ngspice, KiCad, Scilab, Verilator) across Windows, Linux, and macOS. Built as a screening task for the FOSSEE Semester Long Internship.

vyges-tools /lvs

Layout-vs-schematic: SPICE netlist comparison with clear divergence diagnostics.

Mysha-Fathima /Physical-Verification-using-SKY130

"10-day VSD Physical Verification workshop using the SKY130 open-source PDK and EDA tools".