axi4-stream 开源项目推荐（31 个）

OSVVM /AXI4

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

mmxsrup /axi4-interface

AX 4和AX 4-Lite接口定义

VHDL /Interfaces

Interface definitions for VHDL-2019.

nelsoncsc /verilaxi

SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte-exact real-image round-trip tests. Verilator · Yosys · Docker · CI.

ReezanVisram /FPGA-RT-Audio-Visualizer

A real-time audio visualizer on an FPGA. Receives and transmits audio packets via I2S, and displays the time-domain waveform of the input signal using VGA. Supports changing waveform and background colours via UART.

rlee287 /hardware-bus-infrastructure

A collection of formal properties for hardware buses, and cores using them.

chaffybird56 /isp-axi4

Verilog image signal processor with AXI4-Stream interfaces — RTL ISP pipeline for FPGA SoC integration.

mmxsrup /data2axi4s

Convert data signal to axi4-stream signal

JN513 /verilog-buses-implementations

Popular bus implementations in Verilog HDL

amamory /hermes-2x2-noc-axis-ip

A 2x2 mesh NoC compatible with AXI streaming interface

Dimakdrshv /UART_Controller

Parametrizable UART controller in Verilog with AXI-Stream interface, configurable baud rate, oversampling ratio, parity mode, stop bits, and regression testbench for verification.

stevenbell /axis_debugger

Lightweight AXI-Stream debugging probe

adamchristiansen /axi5-pid-controller

An AXI4/5-Stream PID controller

teo1747 /zedboard-vga-video-pipeline

Real-time VGA video chain on the ZedBoard (Zynq-7000): test pattern, AXI4-Stream, Vitis HLS inverter and overlay IPs, 640x480 output

Ajayyyyyyyyyyy /axi-stream-bridge-uvm-verification

Original UVM verification environment for a fictional AXI4-Stream-to-internal-bus bridge IP (StreamBridge) -- tag-indexed scoreboarding, split completer/DMA environments, wide-bus lane checking.

adamchristiansen /axi5-ema-filter

An AXI4/5-Stream exponential moving average (EMA) filter

billdmar /fifo-verification-suite

8 SystemVerilog FIFO designs formally verified (SymbiYosys BMC + k-induction), mutation-tested, FPGA-characterized — green CI

ayoub-ac /fir-filter-fpga-core

Parametric FIR filter IP core in SystemVerilog. Transposed direct-form, AXI4-Stream, bit-exact vs scipy.signal.lfilter. For DSP/SDR/audio/ML.

amamory /axi_noc_counter_ip

A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source

EMBKSM /gonghack-PL

FPGA PL 부분, I2C FSM로직 구현 및 AXI-Lite와 AXI-Stream을 이용해서 DMA구현, AI연산을 DPU로 구현해 AI를 하드웨어로 가속