osvvm 开源项目推荐（20 个）

VLSI-EDA /PoC

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

OSVVM /OSVVM

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

OSVVM /AXI4

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

OSVVM /OsvvmLibraries

该项目在 GitHub 上没有填写描述

PacoReinaCampo /MPSoC-DV

Multi-Processor System on Chip verified with UVM/OSVVM/FV

PacoReinaCampo /SoC-DV

System on Chip verified with UVM/OSVVM/FV

tmeissner /libvhdl

Library of reusable VHDL components

wyvernSemi /Articles

Collected article documents in PDF covering subject with co-simulation, embedded systems, software development and logic design and verification

nselvara /chipdev.io

This repository contains VHDL implementations for all hardware design challenges (quests/questions) featured on the chipdev.io website.

OSVVM /VerificationIP

Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.

BekdoucheAmine /osvvm-modelsim-ci-cd-template

A GitHub template repository for quickly creating VHDL/FPGA projects with a standardized structure and preconfigured CI/CD workflows, including OSVVM support.

jgonmor16 /hdlsnip.nvim

Parameterised VHDL templates for Neovim — entities, FSMs, CDC, AXI4-Lite and testbenches, rendered from Lua rather than pasted.

PacoReinaCampo /PU-DV

Processing Unit verified with UVM/OSVVM/FV

nselvara /HDL-Core-Library

Reusable HDL modules, packages, and testbench utilities for FPGA and ASIC development, supporting both VHDL and Verilog.

nselvara /VHDL-Utils

A VHDL code base that contains Utility Packages for both HDL and Testbenches

edaa-org /pyEDAA.OSVVM

Parsing and Converting OSVVM Specific Data Formats.

MatthieuMichon /boiler-plate-ghdl-osvvm

该项目在 GitHub 上没有填写描述

angeliaplutus /ipcoredesign

Design & Verification of IP Cores and ICs, Artificial Intelligence

IPCore-Tests /AXI

该项目在 GitHub 上没有填写描述

PacoReinaCampo /OSVVM

Open Source VHDL Verification Methodology