uvm 开源项目推荐（487 个）

cocotb /cocotb

cocotb: Python-based chip (RTL) verification

openhwfoundation /core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

maximecb /uvm

Fun, portable, minimalistic virtual machine.

taichi-ishitani /tvip-axi

AMBA AXI VIP

chipsalliance /Surelog

SystemVerilog 2017 预处理器、解析器、Elaborator、UHDM 编译器。提供IEEE Design/TB C/C++ VPI以及Python、AST和UHDM API。在 Linux gcc、Windows msys2-gcc 和 msvc、OsX 上编译

rggen /rggen

Code generation tool for control and status registers

troyguo /awesome-dv

Awesome ASIC design verification

tymonx /logic

用于创建、构建和测试针对FPGA和ASIC的RTL项目的CMake、SystemVerilog和SystemC工具。

Nic30 /hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

SystemRDL /PeakRDL

Control and status register code generator toolchain

taichi-ishitani /tnoc

Network on Chip Implementation written in SytemVerilog

Juniper /open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

kumarrishav14 /AXI

AXI协议的VIP服务

brekkylab /ailoy

The open-source agent SDK that gives every agent its own VM. Each VM is a microVM sandbox where the agent installs software, runs code and uses the GPU. Python, Node.js and Rust.

Quang-Minh-Phung /DienTu_TKVM_Documents

该仓库涵盖基础电子学到集成电路设计，重点是前端（RTL/DV）。在电子专业中融入其他职业方向的额外知识。由明宇（蓬光明）编纂。

gokeshenzhen /TraceWeave

简洁的测试平台日记，波浪（FSDP/BCD），根因分析HCP服务器.一款简单且通用的LCP服务器，通过日志解析和波形分析（FZB/BCD）来应对测试台模拟故障

gupta409 /Processor-UVM-Verification

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

erihsu /INT_FP_MAC

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

nelsoncsc /ISP_UVM

A Framework for Design and Verification of Image Processing Applications using UVM

Siddhi-95 /AHB-to-APB-Bridge-Verification

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.