amba-axi 开源项目推荐（14 个）

taichi-ishitani /tvip-axi

AMBA AXI VIP

taichi-ishitani /tnoc

Network on Chip Implementation written in SytemVerilog

kumarrishav14 /AXI

AXI协议的VIP服务

sean-galloway /RTLDesignSherpa

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

RISMicroDevices /OpenNCB

开源非相干CHI桥（CHI SN-F到AXI-4桥）

OpenXiangShan /OpenNCB

开源非相干CHI桥（CHI SN-F到AXI-4桥）

krailis /zynq-axi-tutorial

A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)

dhruvalmistry2007 /axi4-lite-register-mapped-peripheral

AXI4-Lite slave in SystemVerilog that exposes control, configuration, status and data registers to a bus master. It handles the five independent channels with proper VALID and READY handshakes, decodes addresses, and returns OKAY or error responses. A master model and protocol assertions verify it in Verilator.

ansh07verma /AXI4-Lite-Protocol-Checker

SystemVerilog AXI4-Lite protocol verification environment featuring a 5-channel monitor, associative-array scoreboard, 13 SVA assertions, functional coverage closure, back-pressure testing, and negative protocol testbench.

aayush062026 /pcie-transaction-layer

PCIe Transaction Layer: TLP arbiter, ECRC/LCRC reference RTL over AMBA AXI.

k-vijay-kumar /Vlsi-Protocols

On-chip and peripheral communication protocols

KaidenHsu /SOPC-System-Design

homework and labs for "SOPC Design Practice and FPGA System Design (2026 Spring)" in NSYSU, Taiwan

AkarshSri34 /AXI-Verification-using-UVM

UVM environment for AMBA AXI4: master agent, reactive slave with memory model, burst write/read-back sequences, random back-pressure and SVA handshake checks.

Archit-y /axi-lite-uvm-verification

UVM verification environment for an AXI4-Lite slave — 4/4 tests passing, 0 errors, up to 100% functional coverage