questasim 开源项目推荐（89 个）

suoto /hdl_checker

重新利用现有的HDL工具来帮助编写更好的代码

Paebbels /JSON-for-VHDL

一个用VHDL实现的JSON库。

MJoergen /HyperRAM

可移植 HyperRAM 控制器

kleverhq /wavepeek

通过CLI检查RTL波形（VCD/FST）的工具

Ghonimo /Pre_Silicon-AHB-to_APB-Verification

针对AHB 2APB Bridge设计的全面验证套件，具有SystemVerilog和基于UVMs的方法论。🌉🚀

wyvernSemi /mem_model

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Noamv7 /Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

该项目专注于数字逻辑电路的设计和验证，特别是针对使用Verilog、SystemVerilog和SVA的芯片设计。主要目标包括设计符合行业标准的模块，如APB（高级外设总线）、内存系统和systolic矩阵乘法。

htminuslab /Modelsim-Unicorn

Modelsim QEMU Unicorn integration via the FLI

NikLeberg /cosim_jtag

Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.

MJoergen /Avalon

Utilities for Avalon Memory Map

wendigp /Development-of-AXI4-Verification-IP-VIP-using-UVM

Configurable AXI4 Verification IP developed using UVM, featuring reusable master and slave agents, protocol checking, functional coverage, and scoreboard-based verification.

Abdelrahman1810 /SPI_Slave_with_Single_Port_RAM

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

Choaib-ELMADI /getting-started-with-systemverilog

Getting started with SystemVerilog: Hardware Description Language for design and verification.

Paebbels /pyIPCMI

A Python-based IP Core Management Infrastructure.

SimplHDL /simplhdl

Simulation and implementation flow for hardware description languages

dave2pi /SublimeLinter-contrib-vlog

SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog

yuravg /eda-scripts

Collection of scripts for EDA tools

teekamkhandelwal /SRAM_Controller

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

Abdelrahman1810 /RTL-Verification-of-AMBA3_4-APB-Protocol

This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.

angrammenos97 /imc

In-Memory Accelerator Controller