logic-design 开源项目推荐（172 个）

DrWaleedAYousef /Teaching

Waleed A博士的教学材料Yousef

ParhamP /Natural_Logic_Interpreter

Automatically interpret and validate nested natural logic arguments based on rules of inference and propositional logic

shayanop /Water-Level-Meter

Water Level Meter

ysyesilyurt /Metu-CENG

All the homeworks, studies and projects I've done at Metu-CENG

beetlex-io /EventNext

EventNext is logic interface design actors components for .net core

ericm /newlogic

Circuit Builder Desktop Application (like mmlogic) made with Electron + React Typescript. Compatible with Windows, Mac and Linux.

dreylago /logicmin

Logic Minimization in Python

kadircet /CENG

All the homeworks, testers and projects done at METU-CENG

venkat-0706 /codemind-c

As an Ignite Coder, solved numerous problems using C programming, demonstrating expertise in algorithms, problem-solving, and efficient coding for technical challenges.

Noamv7 /Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

该项目专注于数字逻辑电路的设计和验证，特别是针对使用Verilog、SystemVerilog和SVA的芯片设计。主要目标包括设计符合行业标准的模块，如APB（高级外设总线）、内存系统和systolic矩阵乘法。

fcayci /sv-digital-design

SystemVerilog examples for a digital design course

tunacinsoy /CSE

All the homeworks, testers and projects done at Marmara University, Computer Science & Engineering

wyvernSemi /Articles

Collected article documents in PDF covering subject with co-simulation, embedded systems, software development and logic design and verification

VitorgsRuffo /Building-The-Hack-Computer

This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.

enesgarip /Projects

Projects of a CSE student at Marmara University

stdgregwar /elve

ELVE : ELVE Logic Visualization Engine

asyncvlsi /chp2prs

Automated conversion from CHP to PRS

AhmedHamed3699 /AES-Encryption

An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog

anthonyabeo /digital_circuits

A collection of digital logic circuits

geitanksha /risc-v-pipelined

Created a RISC-V Pipelined processor in SystemVerilog with features like Caches, Prefetching, History Table. Skills employed: SystemVerilog, Verdi, Logic Design, Computer Architecture