Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

该项目专注于数字逻辑电路的设计和验证，特别是针对使用Verilog、SystemVerilog和SVA的芯片设计。主要目标包括设计符合行业标准的模块，如APB（高级外设总线）、内存系统和systolic矩阵乘法。

  • 语言Verilog
  • 大小30.9 MB
  • 更新2024年6月26日
在 GitHub 打开
avatarNoamv7
14
40

项目介绍

Noamv7/Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification 是一个托管在 GitHub 上的开源项目，主要使用 Verilog 编写，目前获得 14 个 Star、4 次 Fork。

仓库全名
Noamv7/Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification
Star 数
14
Fork 数
4

README 摘要

Matrix Multiplication Using Systolic Arrays This repository contains the Verilog code for a matrix multiplication design implemented using systolic arrays. The project is divided into two main parts: the Design Part and the Verification Part. Design Part The Design Part focuses on the implementation of the matrix multiplication algorithm using systolic arrays. Various modules including the APB slave, memory,…

完整内容见 GitHub 原始 README 或本页 。

常见问题

Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification 用什么语言开发？

主要使用 Verilog 编写，目前有 14 个 Star。

如何获取 Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification 的源码？

可以直接克隆仓库：git clone https://github.com/Noamv7/Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification.git；安装与运行步骤见仓库 README。

Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification 最近还在维护吗？

仓库最近一次更新为 2024年6月26日，当前没有未关闭的 Issue；Star 数为 14，可作为社区活跃度的参考。

本页面展示项目元数据与原始 README，GitRead 中文社区 编辑团队负责选题收录。

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关于

GitHub 原始描述（英文）

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

描述取自 GitHub 官方 API，保持仓库作者书写的原文。

简要分析

热度分
36
价值分
11
活跃状态
活跃
amba-apbchip-designfunctional-coveragelogic-designmatrix-multiplicationquestasimsvasystemverilogsystolic-arraysverificationverilog
GitHub

语言占比

Python
SystemVerilog
Verilog

贡献者

Noamv7Noamv7

README

Matrix Multiplication Using Systolic Arrays

This repository contains the Verilog code for a matrix multiplication design implemented using systolic arrays. The project is divided into two main parts: the Design Part and the Verification Part.

Design Part

The Design Part focuses on the implementation of the matrix multiplication algorithm using systolic arrays. Various modules including the APB slave, memory, processing elements (PE), and the main matrix multiplication calculation module are implemented in Verilog. These modules interact to perform matrix multiplication efficiently.

Verification Part

The Verification Part aims to ensure the correctness and functionality of the matrix multiplication design through rigorous verification techniques. Simulation-based testing, functional checking, functional coverage analysis, and comparison with a Python-based golden model are conducted to validate the design under various conditions and inputs.

Repository Contents

  • Design Part:

    • Verilog modules for APB slave, memory, processing elements, and matrix multiplication calculation.

  • Verification Part:

    • Header and package files containing system parameters and definitions.
    • Testbench, tester, functional checker, and functional coverage modules for verification.
    • Python-based golden model for comparison.

Interface Information

The matmul_interface.sv file defines the interface for communication between the design and the testbench. It includes signals for clock, reset, control, and data transmission.

Usage

  1. Design Part: Instantiate and interconnect the design modules according to system requirements. Ensure proper clocking and reset signals for correct functionality.

  2. Verification Part: Run simulation-based testing using the provided testbench and modules. Monitor functional behavior using the functional checker and analyze coverage metrics using the functional coverage module.

Conclusion

This project presents an efficient implementation of matrix multiplication using systolic arrays, accompanied by thorough verification to ensure accuracy and reliability.

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