functional-coverage 开源项目推荐（81 个）

chiselverify /chiselverify

A dynamic verification library for Chisel.

fvutils /pyvsc

Python packages providing a library for Verification Stimulus and Coverage

tmeissner /psl_with_ghdl

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

fvutils /pyucis

Python API to Unified Coverage Interoperability Standard (UCIS) Data

Noamv7 /Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

该项目专注于数字逻辑电路的设计和验证，特别是针对使用Verilog、SystemVerilog和SVA的芯片设计。主要目标包括设计符合行业标准的模块，如APB（高级外设总线）、内存系统和systolic矩阵乘法。

Yashas2801 /UART-Verification-using-UVM

UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.

wendigp /Development-of-AXI4-Verification-IP-VIP-using-UVM

Configurable AXI4 Verification IP developed using UVM, featuring reusable master and slave agents, protocol checking, functional coverage, and scoreboard-based verification.

zlsjtj /apb-uart-fifo-uvm

Learn independent UVM checking with APB-UART, async FIFOs, and reproducible fault-injection examples.

gopro-uvm-rtl-verification /RISC-V-CPU-Core-UVM-Based-ISA-Compliance-Verification

RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

Vivek-Dave /UVM_TestBench_For_S_R_Latch

Simple and Complete UVM TestBench For Verification Of S R Latch

gopro-uvm-rtl-verification /Async-Fifo-Cdc-Uvm-Verification

UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.

TatsuProject /rvgen

Pure-Python RISC-V instruction generator with built-in functional coverage, auto-regression, and CI-ready dashboards.

Tharunreddym /riscv-pipeline-verification

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

abdo-ehab-euv /sram-controller-uvm-verification

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

harishchittaragi /DVFT11

Hands-on Design Verification — SystemVerilog testbenches, full UVM environment for APB Protocol, Python scripting, SVA assertions & functional coverage. Trained at ChipEdge using Synopsys VCS.

dhruvalmistry2007 /systemverilog-assertions-functional-coverage-framework

Reusable SystemVerilog verification framework that pairs immediate and concurrent assertions with functional coverage. Protocol and reset checks flag violations at the exact failing cycle, while covergroups, coverpoints and cross coverage show which scenarios the tests still miss. Checkers attach to any design through bind.

wendigp /AHB_APB_Bridge_Verification

UVM-based verification of an AHB-to-APB bridge, validating protocol compliance, address decoding, data integrity, error handling, and corner cases using constrained-random testing and functional coverage.

iceTo1 /sv-pipelined-cpu-uvm

Custom 16-bit 3-stage pipelined CPU in SystemVerilog with UVM verification, RAW hazard handling, assertions, constrained-random testing, and functional coverage.

woodrowb96 /riscv-rtl-and-verification

RV32I RISC-V core written in SystemVerilog, with an emphasis on coverage-driven verification using constrained-random stimulus, SVA assertions, and functional coverage

ScottyB55 /I2C_Chip_Verification

UVM verification environment for an I2C controller (constrained-random + assertions + functional coverage) — Questa/ModelSim