degital-design 开源项目推荐（16 个）

bjwanneng /veriflow-cc

VeriFlow-CC：一个基于Claude代码的RTL设计流水线。利用有状态、零依赖的LLM编排技能，自动化Chip-on-Chat从架构到综合（iVerilog/Yosys）。具备子代理嵌套功能，用于代码生成和行为驱动的验证。

Abdelrahman1810 /RTL-Verification-of-AMBA3_4-APB-Protocol

This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.

rogerhao66666 /I2C-controller

该项目在 GitHub 上没有填写描述

JuanCantu1 /Mesh-NoC-Router

Parameterizable mesh NoC router in SystemVerilog: virtual channels, deadlock-free virtual networks, tile-boundary security, two-stage pipeline. Verified with scoreboards, mutation testing and formal proofs; synthesized on sky130.

Himanshi-Bhere /aes-fpga-encryption

Verilog-based AES-128 encryption implementation for FPGA platforms, featuring key expansion and core AES transformations. Designed for RTL simulation, hardware deployment, and exploration of cryptographic hardware security.

laxmiulavi /Verilog-RTL-30Days

30 Days Verilog RTL Design Challenge | Verilog | Testbenches | Digital Design | GTKWave | Icarus Verilog |VLSI | RTL Design |

lyraaupadhyay /verilog-processor-datapath

A collection of Verilog HDL modules developed while building a processor datapath, including an ALU, Register File, and integrated datapath components with simulation and synthesis.

shreekanthkapparagaon /uart-verilog-transceiver

A modular UART (8N1) serial transceiver in Verilog featuring configurable baud rate, framing error detection, self-checking verification, waveform validation, and GitHub Actions CI.

mohamedhamdy2f /ALU-16bit

A fully combinational 16-bit ALU supporting 20 arithmetic, logic, and shift/rotate operations, built in Verilog

vallala-saikumar /I2C_PROTOCOL---VERILOG

Verilog implementation of the I2C protocol featuring Master, Slave, RTL integration, and functional verification using a custom testbench.

Yaswanthreddy-696 /Synchronous-FIFO-Verilog

RTL implementation of a parameterized synchronous FIFO in Verilog HDL with read/write operations, full and empty flag generation, overflow and underflow detection, and comprehensive testbench simulation using ModelSim.

YashKhodre /UART-Communication-System

A Verilog HDL implementation of a UART communication system featuring a baud rate generator, transmitter, receiver, and end-to-end loopback verification.

mrchowdhury880-commits /New-resposltory-

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khaled759 /UART

UART VHDL code with programmable baud rate

gitfahadahmad /apb-verification

AMBA APB protocol verification suite in SystemVerilog and UVM. Features a mailbox-based layered testbench for a 256-word slave and a complete UVM environment for a multi-block APB peripheral (registers, timer, FIFO, RAM) with 100% functional coverage and constrained-random stimulus. Simulated using Cadence Xcelium.

RjSarkar83 /Brand_Designer

Ranjan Sarkar – Visual Brand Designer 2025