amba-apb 开源项目推荐（25 个）

sean-galloway /RTLDesignSherpa

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

MohamedHussein27 /AMPA_APB4_Protocol

This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory, and comprehensive testbenches. Includes scripts for fast simulation and synthesis using QuestaSim, Vivado and Quartus Prime

Noamv7 /Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

该项目专注于数字逻辑电路的设计和验证，特别是针对使用Verilog、SystemVerilog和SVA的芯片设计。主要目标包括设计符合行业标准的模块，如APB（高级外设总线）、内存系统和systolic矩阵乘法。

Karan-nevage /APB-Protocol-Using-Verilog

Design and verification of the Advanced Peripheral Bus (APB) protocol using Verilog. Includes Verilog modules for APB operations and a testbench for verifying functionality and compliance with protocol standards.

dhruvalmistry2007 /amba-apb4-gpio-timer-subsystem

APB4 slave peripheral block in SystemVerilog that puts a GPIO controller and a programmable timer behind one register map. A bus master configures pins and the timer with ordinary read and write transfers, and protocol assertions check every transaction. Simulated with Verilator and GTKWave, synthesized with Yosys.

kaushanr /System-Bus-Design

Design of a system bus architecture - Team Project @ ENTC UoM

ubyhzargam /AMBA-Protocol-Family

This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm

Saad1507 /amba-apb-transceiver

AMBA APB Master-Slave protocol implementation in Verilog with zero-wait and wait-state support.

sidhantp1906 /AMBA4-APB

Advanced Pheripheral Bus design using verilog HDL

fjpolo /Verilator_FormalVerification

SymbiYosys (sby) Formal Verification

Ashika005 /AMBA-APB-UART-Controller

Verilog RTL implementation of a bidirectional AMBA APB-to-UART controller featuring configurable baud rates, double-flop RX synchronization, and GTKWave verification.

S-Steven-Joshua /JS-SoC

32-bit single-cycle RISC-V SoC in SystemVerilog featuring an APB interconnect, UART, PWM, Timer and I2C peripherals, and a Java-based control-word generator for memory-mapped peripheral configuration.

Gagandeep-25 /APB_RAM

APB RAM RTL design with full UVM-based verification using constrained-random testing.

DamiProject /Digital-Design

VHDL RTL design exercises covering counters, synchronization, FSM control and APB integration.

RamnarayanBalai /UART-Design-Verification

A synthesizable UART design with an AMBA APB3 slave interface. Verified using SystemVerilog, Assertions (SVA), and functional coverage.

cong2738 /SmartFarmSensorSystem

Smart Farm Sensor System with AMBA APB Interface my RISC-V

harinisubbiah /Leon3_Processor_WithGRETH_Verfication

Functional Verification, ASIC Synthesis and Formal Verification of an AMBA Memory Interface Bridge integrated with the LEON3 Processor and GRETH Ethernet MAC.

GauthamMK-0 /GPIO-core

RTL implementation of GPIO core compatabile AMBA APB v3 protocol

vohoangnguyennnn /APB4-ip-framework

AMBA APB4 peripheral framework with reusable protocol logic, register bank, GPIO/Timer examples, and UVM verification.

pav-kum-07 /APB_VIP

AMBA APB3 UVM Verification IP — parameterized SystemVerilog VIP with 100% functional coverage and SVA checks