VLSI-Design-Verification-Projects

🔍 VLSI Design Verification Projects

Welcome to my collection of VLSI Design Verification projects.
This GitHub repository showcases hands-on work in functional verification using Verilog, SystemVerilog, UVM, Protocols, and industry-standard EDA tools.

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📁 Repository Structure

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├── ALU_32bit_UVM/               # 32-bit ALU Design using Verilog + UVM Verification
│   ├── rtl/
│   ├── tb/
│   └── README.md
│
├── AXI4_Protocol_Verification/           # AXI4 Protocol Verification
│   ├── Design/
│   ├── Testbench Components/
│   └── README.md
│
├── AHB_Protocol_Checker/        # AHB Protocol
│   ├── Design/
|   ├── Testbench/
│   └── README.md
│
├── Design_and_Verification_of_AXI4-lite_Slave_Protocol/          # AXI4-lite Slave Protocol with Verilog and FSM-based Testbench
│   ├── Design/
│   ├── tb/
│   └── README.md

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🧪 Key Verification Skills Demonstrated

• ✅ UVM Environment Development (agent, monitor, driver, scoreboard)
• ✅ Functional Coverage and Constrained Random Testing
• ✅ Assertion-Based Verification (SVA)
• ✅ SystemVerilog Interface & Clocking Block Usage
• ✅ Directed & Randomized Testing
• ✅ Testbench Reusability & Modularity
• ✅ Scoreboarding and Functional Checks
• ✅ Simulation with ModelSim/QuestaSim

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🧰 Tools Used

• QuestaSim / ModelSim / Synopsis VCS / Cadence Xcelium – Simulation
• SystemVerilog – Design & Verification Language
• UVM (Universal Verification Methodology) – Verification Framework
• Git/GitHub – Version Control & Collaboration

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🤝 Let’s Connect

If you’re a recruiter, engineer, or enthusiast, I’d love to connect!

• 🌐 LinkedIn
• ✉️ [email protected]

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📜 License

MIT License. Free to use with attribution. Contributions welcome!

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🚀 Built with curiosity and passion for VLSI Design Verification.