design-verification 开源项目推荐（152 个）

Lramseyer /vaporview

Waveform Viewer Extension for VScode

kumarrishav14 /AXI

AXI协议的VIP服务

heyfey /sv-pathfinder

VS Code extension for SystemVerilog design navigation, RTL tracing, schematic viewer, and waveform integration

SACHINUR17 /VLSI-Design-Verification-Projects

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

gokeshenzhen /gen-tb-skill

Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP spec and register table, with a UVM-sequence flow for DV and a tb_api:: task BFM for DE.

kumarrishav14 /AMBA_APB

To design test bench of the APB protocol

ed766 /ucie_chiplet_soc

Firmware-driven dual-die RV32 chiplet SoC with GCC/ISS co-verification, DMA/AES offload, UPF 4.0 low-power intent, async CDC, real UVM, formal, and open-source coverage.

williaml33moore /bathtub

BDD Gherkin implementation in native SystemVerilog, based on UVM.

jiru1997 /UVM-examples-and-source-code

uvm examples and source code

kumarrishav14 /ALU_UVM

UVM Test bench for a 8-bit ALU

zlsjtj /apb-uart-fifo-uvm

Learn independent UVM checking with APB-UART, async FIFOs, and reproducible fault-injection examples.

ShwetaKiranTotla /Micro-processor-Design-Verification

Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.

bvsnithin /hardware-interview-prep

A repository to store some code snippets for hardware interview prep.

zanwei /harness-design

Design DNA Phase 3 verification harness — scores fidelity (tokens, style, effects) and drives a correction loop until ship-ready.

kumarrishav14 /I2C

VIP for I2C

sashakatne /nvfp4-dotprod-formal-dv

Formal (VC Formal FPV) and UVM verification of an 8-lane mixed-precision INT8/BF16/NVFP4 dot-product core, with a shared SystemVerilog golden reference across assertions and scoreboards.

badimirzai /architon-cli

Deterministic hardware verification engine that fails CI when connected components violate electrical or interface contracts.

dvtalk /dvtalk.github.io

该项目在 GitHub 上没有填写描述

opendv360 /verification-diagrams

This collection of verification diagrams is created to help educators, students, and engineers visualize complex hardware verification concepts. These illustrations transform complex concepts into understandable visuals.

dg2300 /AXI_WB_TB

Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.