alu 开源项目推荐（434 个）

zslwyuan /Basic-SIMD-Processor-Verilog-Tutorial

Verilog 中实现了一个简单的 SIMD 处理器，核心是一个 16 位的 SIMD 算术逻辑单元。2 的补算计算在本算术逻辑单元中实现。算术逻辑单元操作将耗时两个时钟。第一个时钟周期用于将值加载到寄存器中。第二个周期用于执行操作。6 位操作码用于选择函数。指令码（包括操作码）将为 18 位。

bharathgs /NALU

Basic pytorch implementation of NAC/NALU from Neural Arithmetic Logic Units paper by trask et.al

DoctorWkt /CSCvon8

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

mirseo /JSilicon

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

ghaiklor /nand-2-tetris

Computer built from the ground up on top of own CPU, while compiler and assembler for it implemented in Rust language

DoctorWkt /CSCv2

Version 2 of my Crazy Small CPU

Johnlon /spam-1

Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu

paranoiaproject /payuclient

Payu ALU service client

edson-acordi /4bit-microcomputer

MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for educational purposes and distributed for free under open-source licenses.

RomeoMe5 /DDLM

《数字合成 ： 实践课程》一书各章节的源代码 （ 第 2 页 ） 。A.Y.A.罗曼诺夫和尤文。潘丘拉 （ Panchula ）

mihir8181 /VLSI-Design-Digital-System

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

timlg07 /NandGame-Solutions

Solutions for all levels of the NandGame.

tmarhguy /alu

8-bit combinational ALU built from scratch with 3,488 CMOS transistors (KiCad + SPICE + Logisim + 1.24M tests

smangul1 /rop

The Read Origin Protocol (ROP) is a computational protocol that aims to discover the source of all reads, including those originating from repeat sequences, recombinant B and T cell receptors, and microbial communities.

princeofpython /Computer-Architecture

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

SACHINUR17 /VLSI-Design-Verification-Projects

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

AsadiAhmad /ALU-8Bit

ALU Verilog Project calculate add, subtract, increment, decrement, multiply

goupaz /lowlevel

Design your own CPU, Operating system, and Compiler (Maintainer: Emin Ghuliev)

hoangsonww /Digital-Design-Labs

🖥️ A collection of SystemVerilog modules and Assembly programs. This repo includes examples of decoders, encoders, binary adders, and interactive games such as Guessing Game implemented in hardware description and assembly languages, illustrating practical applications in digital systems and microprocessor interfacing.

clemgoub /TypeTE

Genotyping of segregating mobile elements insertions