verilog-project 开源项目推荐（345 个）

Gowtham1729 /Image-Processing

Verilog 图像处理工具箱，使用 Basys3 FPGA

snbk001 /Verilog-Design-Examples

Verilog 设计示例，带有自检测试平台。半叠加器、全加法器、多路复用器、算术逻辑单元、D触发器、使用Mealy机和Moore机的序列检测器、1的数量、二进制转灰制转换、上下计数器、时钟分频器、PIPO、n位通用移位寄存器、4位LFSR、单端口RAM、双端口RAM、同步先进先出、异步先进先出、8x8顺序乘法器

zslwyuan /Basic-SIMD-Processor-Verilog-Tutorial

Verilog 中实现了一个简单的 SIMD 处理器，核心是一个 16 位的 SIMD 算术逻辑单元。2 的补算计算在本算术逻辑单元中实现。算术逻辑单元操作将耗时两个时钟。第一个时钟周期用于将值加载到寄存器中。第二个周期用于执行操作。6 位操作码用于选择函数。指令码（包括操作码）将为 18 位。

michaelehab /AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

neelkshah /MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

prajwalgekkouga /AHB-to-APB-Bridge

AHB到APB桥是一个AHB从站，也是唯一一个在高速AHB和低功率APB之间提供接口的APB主机。AHB上的读写传输转换为APB上的等效传输。

adibis /DDR2_Controller

DDR2 memory controller written in Verilog

mongrelgem /Verilog-Adders

Implementing Different Adder Structures in Verilog

Akashtailor-exe /30-days-of-verilog

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

xiazhuo /nscc2022_personal

NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）

ashishrana160796 /verilog-starter-tutorials

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

TheSUPERCD /8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

yigitbektasgursoy /SDRAM_Verilog

Verilog HDL implementation of SDRAM controller and SDRAM model

Arjun-Narula /Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

mihir8181 /VerilogHDL-Codes

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

vedic-partap /Computer-Organization-and-Architecture-LAB

Solution to COA LAB Assgn, IIT Kharagpur

SACHINUR17 /VLSI-Design-Verification-Projects

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

coole198669 /viterbi_decoder

Hardware Viterbi Decoder in verilog

adibis /Interrupt_Controller

An 8 input interrupt controller written in Verilog.

sarthak268 /Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.