verilog-hdl 开源项目推荐（941 个）

ultraembedded /cores

各种HDL（Verilog）IP核

VUnit /vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

PyHDI /Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

dpretet /async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

mshr-h /vscode-verilog-hdl-support

Verilog/SystemVerilog 对 VS Code 的支持

NNgen /nngen

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

PyHDI /veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

ultraembedded /core_jpeg

High throughput JPEG decoder in Verilog for FPGA

Gowtham1729 /Image-Processing

Verilog 图像处理工具箱，使用 Basys3 FPGA

snbk001 /Verilog-Design-Examples

Verilog 设计示例，带有自检测试平台。半叠加器、全加法器、多路复用器、算术逻辑单元、D触发器、使用Mealy机和Moore机的序列检测器、1的数量、二进制转灰制转换、上下计数器、时钟分频器、PIPO、n位通用移位寄存器、4位LFSR、单端口RAM、双端口RAM、同步先进先出、异步先进先出、8x8顺序乘法器

AUCOHL /Fault

A complete open-source design-for-testing (DFT) Solution

thedatabusdotio /fpga-ml-accelerator

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

ben-marshall /uart

A simple implementation of a UART modem in Verilog.

michaelehab /AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

jiwoonl /Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA

Energy-efficient Event-driven Spiking Neural Network accelerator for FPGA with PyTorch integration

neelkshah /MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

ekb0412 /100DaysofRTL

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

gupta409 /Processor-UVM-Verification

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

aptx1231 /BUAA_CO

2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)

RISC-KC /basic_rv32s

教学用 RISC-V 处理器设计框架：从单周期到 5 级流水线，包含 FPGA 验证和完整学习指南！一份 RISC-V CPU 设计指南。