MIT License

项目介绍

kumarrishav14/AXI 是一个托管在 GitHub 上的开源项目,主要使用 SystemVerilog 编写,采用 MIT License 许可证,目前获得 187 个 Star、43 次 Fork。

仓库全名
kumarrishav14/AXI
开源许可证
MIT License
Star 数
187
Fork 数
43
未关闭 Issue
5

README 摘要

AXI VIP for AXI Protocol Architecture Components 1. Sequence item 2. Sequence - 2 sequence were made as in AXI read and write can happen in parallel. 3. Sequencer - 2 Sequencer were connected to a single driver so that the read and write operation are independent of each other and can happen in parallel 4. Driver - One each in master and slave 5. Monitor - One each in master and slave 6. Scoreboard 7. Environment 8…

完整内容见 GitHub 原始 README 或本页 。

常见问题

AXI 用什么语言开发?

主要使用 SystemVerilog 编写,采用 MIT License 许可证,目前有 187 个 Star。

AXI 可以免费商用吗?

仓库采用 MIT License 许可证,可免费使用与修改,商业使用请遵守许可证条款(例如保留版权声明与许可声明)。

如何获取 AXI 的源码?

可以直接克隆仓库:git clone https://github.com/kumarrishav14/AXI.git,默认分支为 main;安装与运行步骤见仓库 README。

AXI 最近还在维护吗?

仓库最近一次更新为 2022年5月24日,当前有 5 个未关闭 Issue;Star 数为 187,可作为社区活跃度的参考。

关于

GitHub 原始描述(英文)

VIP for AXI Protocol

描述取自 GitHub 官方 API,保持仓库作者书写的原文。

简要分析

热度分
276
价值分
125
活跃状态
活跃

语言占比

SystemVerilog

Release

贡献者

README

AXI

GitHub release (latest by date)

VIP for AXI Protocol

Architecture

Architecture

Components

  1. Sequence item
  2. Sequence - 2 sequence were made as in AXI read and write can happen in parallel.
  3. Sequencer - 2 Sequencer were connected to a single driver so that the read and write operation are independent of each other and can happen in parallel
  4. Driver - One each in master and slave
  5. Monitor - One each in master and slave
  6. Scoreboard
  7. Environment
  8. Test - Comprises of one base test, and 5 directed test cases.
  9. TestBench top - Environment can be configured from here
  10. Configuration Object:
    • env_config - Config object to configure the environment and agents
    • test_config - Config object to configure the test.

How to use

  • Download the latest release from below or visit the release page for more old release.
  • Copy the contents in a folder.
  • Compile tb_top.sv in any simulator and simulate top module.
  • Different test classes can be selected using +UVM_TESTNAME directive.

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