ghdl 开源项目推荐（159 个）

ghdl /ghdl

VHDL 2008/93/87 模拟器

olofk /edalize

用于接口EDA工具的抽象库

suoto /hdl_checker

重新利用现有的HDL工具来帮助编写更好的代码

jakubcabal /spi-fpga

SPI master and SPI slave for FPGA written in VHDL

openlab-x /OpenCircuitX

Free, open-source EDA platform for VHDL and Verilog. HDL editor, circuit canvas, RTL viewer, waveform viewer, and FPGA toolchain in one window.

wyvernSemi /pcievhost

PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

PyFPGA /pyfpga

一个用于程序化使用 FPGA 开发工具的 Python 包。

jakubcabal /uart-for-fpga

Simple UART controller for FPGA written in VHDL

stnolting /neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

stnolting /neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

VHDL /PoC

IP Core Library - Published and maintained by the Open Source VHDL Group

Paebbels /JSON-for-VHDL

一个用VHDL实现的JSON库。

tmeissner /psl_with_ghdl

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

mnemocron /my-discrete-fpga

My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.

Stokpan /E80

Educational VHDL computer with a single-click toolchain for assembly, simulation, and execution on FPGAs

ghdl /docker

Scripts to build and use docker images including GHDL

tmeissner /formal_hw_verification

Trying to verify Verilog/VHDL designs with formal methods and tools

dbhi /vboard

Virtual development board for HDL design

tmeissner /cryptocores

cryptography ip-cores in vhdl / verilog

stnolting /neorv32-riscof

✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.