system-verilog-testbench 开源项目推荐（9 个）

SACHINUR17 /VLSI-Design-Verification-Projects

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

muhammadtalhasami /sv_verilator

System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .

theteamonk /Dual-Port-RAM-4096x64

Dual Port RAM - Verification in System Verilog and Functional Coverage

PRADEEPCHANGAL /Async-FIFO-Verification-Using-UVM

Async FIFO verification using UVM testbench

DorsaAk /combo_fp_adder

🧪"A Simple Hands-On Project": A fully combinational Verilog implementation of IEEE-754 single-precision floating point addition

DorsaAk /MIPS-single-cycle-processor

📚"Major Course Assignment": MIPS Single-Cycle Processor: Implementation in Verilog + Confirmation on Zynq SoC via Xilinx Vivado

DorsaAk /serial_transceiver_moore_fsm

🧪"A Simple Hands-On Project": A simple UART-inspired serial transceiver implemented as a Moore FSM (An exercise of typedef enum, timescale and signed/unsigned numbers in Verilog)

DorsaAk /RTL-timing-analysis

🧪"A Simple Hands-On Project": Timing analysis of a pre-defined digital sequential circuit (critical paths, clk skew, hold/setup violations)

nithinnj93 /vlsi-smart-irrigation-system

VLSI-oriented Smart Irrigation Controller featuring Verilog RTL modules, self-checking testbenches, FSM-based control, and planned ESP32 IoT integration.