vlsi-project 开源项目推荐（30 个）

mihir8181 /VLSI-Design-Digital-System

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

tharunchitipolu /Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

hibagus /64pointFFTProcessor

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

SACHINUR17 /VLSI-Design-Verification-Projects

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

karthik-r-rao /VLSI_Physical_Design_Tool

A simple tool to demonstrate the physical design steps of VLSI Design Flow.

harshithsn /Fault-collapsing-and-Fault-simulation

This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsing, Parallel fault simulation, Deductive fault simulation.

harshithsn /SCOAP-Controllability-and-Observability

This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs SCOAP Controllability and Observability of circuit..

tharunchitipolu /SHA-256-Verilog-HDL

SHA-2 (Secure Hash Algorithm 2), of which SHA-256 is a part, is one of the most popular hashing algorithms out there.

Kethasriramya2912 /Btech_Projects

I've delved into leveraging my academic prowess to drive projects that contribute to my career advancement.

gmurro /VLSI

Very Large Scale Integration project for CDMO class at @unibo

Lomne22339 /IIITD_Resources

A curated collection of study resources, previous year papers, notes, assignments, labs, and projects for IIIT Delhi students.

lolloloschi97 /Very-Large-Scale-Integration

Very Large Scale Integration solved using Costraint Programming and Minizinc

umeshchess /sync-fifo-verilog

Synchronous FIFO

Rushikesh-Dandgawhal /Alarm_Clock

Digital Alarm Clock in Verilog HDL | FSM | ModelSim | Intel Quartus Prime | FPGA RTL Design

kiranlp /Digital-Stop-watch-using-VHDL

Digital Stopwatch – VHDL FPGA Implementation Technologies: VHDL, Xilinx ISE, FPGA, 7-Segment Display • Designed a fully functional VHDL digital stopwatch on FPGA with counter, control (start/stop/reset), and 7-segment display modules, demonstrating mastery of hardware description languages and FPGA synthesis workflows.

raviranjan-vlsi /AMBA-AHB-Master-Slave-Interface-

Verilog implementation of AMBA AHB Master and Slave with FSM control, FIFO integration, burst transfer (INCR4), and waveform-based protocol verification.

DanishAnsari-09 /ZebraZ-2Bit

A 2 Bit Microprocessor unit

raviranjan-vlsi /async-fifo-verilog

Parameterized asynchronous FIFO in Verilog using Gray-coded pointers and 2-stage synchronizers for reliable clock domain crossing, with Full, Empty, Almost-Full and Almost-Empty flags.

gvr-04 /fifo

该项目在 GitHub 上没有填写描述

pushpraj06-Hub /FPGA-Driven-Vertical-Transport-Control-System

FPGA-based multi-floor elevator prototype using Verilog HDL, Vivado, and Xilinx Artix-7 Nexys 4 FPGA Developement Board.