system-verilog 开源项目推荐（186 个）

verilator /verilator

Verilator 开源 SystemVerilog 仿真器和 lint 系统

tscheipel /HaDes-V

HaDes-V 是用于学习微控制器设计的开放教育资源。它引导你使用 SystemVerilog 和 FPGA 工具创建流水线式 32 位 RISC-V 处理器。该资源由 TU Graz 的 EAS Group 开发，将硬件/软件协同设计中的动手练习与在 Basys3 FPGA 板上的实际实现相结合。

esynr3z /corsair

Control and Status Register map generator for HDL projects

nxbyte /Verilog-Projects

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

Weiyet /RTLStructLib

RTL data structure

RomeoMe5 /DDLM

《数字合成 ： 实践课程》一书各章节的源代码 （ 第 2 页 ） 。A.Y.A.罗曼诺夫和尤文。潘丘拉 （ Panchula ）

jtgebert /fpganes_release

Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog

weiber2002 /ICRTL-Benchmark

ICRTL Benchmark: Industrial-level RTL design challenges for evaluating PPA optimization, code generation, and LLM applications in EDA.

eniokaljic /openENOC

openENOC is an open-source Ethernet-based NoC for scalable MPSoC systems, using Layer-2 frame switching to connect CPUs, accelerators and peripherals for crypto, AI and edge computing.

sean-galloway /RTLDesignSherpa

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

cvonk /FPGA_SPI

Connecting FPGA and Arduino using SPI.

Amirarsalan-sn /RISCV-multi-cycle-processor

A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL

pfnet-research /ATPG4SV

A prototype of Concolic Testing engine for SystemVerilog, developed as part of PFN summer internship 2018.

Awais-Asghar /Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).

kinap /AES-Processor

AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.

pulp-platform /trace_debugger

Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.

zeynepCankara /Computer_Organization_Labs

My solutions for Bilkent University CS224 Computer Organization Labs (Spring 2019). Includes assembly programming assignments together with various processor designs in System Verilog HDL

esynr3z /pyhdlsim

Example of Python and PyTest powered workflow for a HDL simulation

Nidhinchandran47 /my_rtl_code

Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

flasonil /Serial-Multiplier

16 bit serial multiplier in SystemVerilog