hardware-software-codesign 开源项目推荐（86 个）

tscheipel /HaDes-V

HaDes-V 是用于学习微控制器设计的开放教育资源。它引导你使用 SystemVerilog 和 FPGA 工具创建流水线式 32 位 RISC-V 处理器。该资源由 TU Graz 的 EAS Group 开发，将硬件/软件协同设计中的动手练习与在 Basys3 FPGA 板上的实际实现相结合。

Yii2004 /TinyCoDesign

Minimal FPGA hardware/software co-design demo with UART protocol, scratchpad memory, and an int8 dot-product accelerator, plus Python/C++ runtimes.

harvard-acc /DreamRAM

DreamRAM: A Fine-Grained Configurable Design Space Modeling Tool for Custom 3D Die-Stacked DRAM

jha-lab /codebench

[TECS'23] A project on the co-design of Accelerators and CNNs.

Electrostat-Lab /Electrostatic-Sandbox

A high-performance infrastructure framework for distributed systems simulation based on the IEEE-1516 HLA Spec. and NASA DSES.

GDSC23BundelkhandUniversity /Google_Solution_Challenge_24

The Google Solution Challenge is an annual competition that invites students and developers to solve real-world problems using Google technologies.This repository is your go-to resource for all the information you need to participate in this exciting solution Challenge.

jha-lab /transcode

[TCAD'23] TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference

changmg /TRAM

Pytorch implementation of TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators

efedemi /riscv-npu-soc

A complete RISC-V SoC in SystemVerilog: pipelined CPU + memory-mapped systolic-array NPU accelerator, running real firmware that offloads a matrix multiply. Includes a small RV32I assembler. Self-checking testbench + CI.

PJHkorea /quantum-mesh-qec

Blueprint for a decentralized, fault-tolerant Surface Code infrastructure leveraging branchless C99 ancilla-syndrome registers, zero-copy C++ binders, and JAX/XLA gradient isolation gates to bypass classical decoding latency walls.

jha-lab /edgetran

[TMC'23] EdgeTran: Device-Aware Co-Search of Transformers and Mobile Platforms

varshinicb1 /AnalogNN

Differentiable Analog Neural Network Simulation — from PyTorch to SPICE. 77.58% Fashion-MNIST, 42/42 SPICE match, scaling law R²=0.9385

yangforever17 /awesome-model-silicon-coevolution

A layer-aware, auditable map of model–software–silicon co-evolution: companion to the survey 'When Models Build Their Own Machines'.

afrozsahar04 /FPGA-based-RISC-V-Processor-Customizable-for-AI-Applications

FPGA-implemented RISC-V processor, evolved from single-cycle to 5-stage pipelined architecture for higher performance and timing efficiency. BRAM-based instruction memory optimizes FPGA usage. Fully FPGA-ready, general-purpose yet tailorable for any AI application, demonstrated with an ML heart rate anomaly detector for wearable AI.

TimurIbrayev /DUB_Sparsity_for_XBars

DUB Sparsity for Crossbars

kenobi314159 /cellular-automaton-fpga

RTL design of Cellular Automaton for FPGA

POPO-so /material-counter

基于 PYNQ-Z2 的小型物料视觉计数系统：FPGA 游程编码、ARM 跟踪计数与 HDMI 显示，附源码、实物照片及复现文档。

preetham-s7 /TileLens

Silicon workbench for chip blueprints, roofline analysis, tile-memory flow, and AI accelerator co-design.

sincerelystepper /Verification-Driven-Embedded-Development

Digital-twin engineering platform for verification-driven edge computing and FPGA-accelerated embedded systems.

rizkysaputradev /Policy-Indexed-Contiguous-Allocation-System

Policy Indexed Contiguous Allocation System (PICAS) is a policy driven and phase aware layered memory allocator with tracing, safety fallbacks, and sanitizer-tested builds.