chisel3 开源项目推荐（124 个）

chipsalliance /chisel

Chisel：一种现代硬件设计语言

SingularityKChen /dl_accelerator

Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions

LoveLonelyTime /Bergamot

An exquisite superscalar RV32GC processor.

agile-hw /lectures

Lectures for the Agile Hardware Design course in Jupyter Notebooks

freechipsproject /diagrammer

Provides dot visualizations of chisel/firrtl circuits

microdynamics-cpu /tree-core-ide

下一代集成开发环境，用于处理器设计和验证。 它支持多硬件语言，支持开源IP管理和易于使用的RTL仿真工具。

howardlau1999 /yatcpu

Yet another toy CPU.

sysprog21 /ca2025-mycpu

RISC-V CPU Labs in Chisel

merledu /nucleusrv

NucleusRV (RV32-IMAFC) - A 32-bit 5 staged pipelined risc-v core.

rhysd /riscv32-cpu-chisel

Learning how to make RISC-V 32bit CPU with Chisel

librecores /riscv-sodor

educational microarchitectures for risc-v isa

rameloni /tywaves-chisel

A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code to values dumped by simulators is now possible thanks to Tywaves!

SYSU-SCC /yatcpu-docs

Documentation for YatCPU

meton-robean /Vector_MulAdd_Accelerator

vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器

thoughtworks /hardposit-chisel3

Chisel library for Unum Type-III Posit Arithmetic

panda5mt /KyogenRV

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

whutddk /Rift2Core

基于 Chisel3，Rift2Core 是一个 9 级、顺序错序、64 位 RISC-V 核心，支持 RV64GC。

mpskex /chisel-npu

Chisel implementation of Neural Processing Unit for System on the Chip

jiegec /fpu-wrappers

Wrappers for open source FPU hardware implementations.

Lampro-Mellon /Quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2