yosys 开源项目推荐（489 个）

The-OpenROAD-Project /OpenLane

OpenLane是一个自动RTL到GDS II流程，基于多个组件，包括OpenROAD、Yosys、Magic、Netgen以及用于设计探索和优化的自定义方法学脚本。

cariboulabs /cariboulite

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

nturley /netlistsvg

draws an SVG schematic from a JSON netlist

olofk /edalize

用于接口EDA工具的抽象库

zachjs /sv2v

SystemVerilog to Verilog conversion

m-labs /nmigen

用于构建复杂数字硬件的全新 Python 工具箱。参见 https://gitlab.com/nmigen/nmigen

efabless /caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

apfaudio /eurorack-pmod

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

openlab-x /OpenCircuitX

Free, open-source EDA platform for VHDL and Verilog. HDL editor, circuit canvas, RTL viewer, waveform viewer, and FPGA toolchain in one window.

PyFPGA /pyfpga

一个用于程序化使用 FPGA 开发工具的 Python 包。

lushaylabs /tangnano9k-series-examples

Examples for the Lushay Labs tang nano 9k series

akilm /Physical-Design

Physical Design Flow from RTL to GDS using Opensource tools.

efabless /caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

chipsalliance /fpga-tool-perf

FPGA tool performance profiling

forflo /yodl

A VHDL frontend for Yosys

ECP5-PCIe /ECP5-PCIe

Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

stnolting /neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

scarv /xcrypto

XCrypto: a cryptographic ISE for RISC-V

multigcs /LinuxCNC-RIO

基于FPGA的LinuxCNC实时IO

dadamachines /doppler

Arduino compatible – Cortex M4F & FPGA Development Board