ddr 开源项目推荐（93 个）

TeamRizu /OutFox

OutFox Alpha 4 LTS / V，Beta I 版本的错误报告库

1a2m3 /SPD-Reader-Writer

SPD 读写器，具备软件写保护功能，支持 Arduino 和 SMBus

afska /piugba

🎮 PIU simulator for the GBA.

RC4ML /Shuhai

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA [FCCM 20]

PrimeMHD /FPGA_ThreeLevelStorage

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

splinedrive /my_hdmi_device

New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

adibis /DDR2_Controller

DDR2 memory controller written in Verilog

iijlab /dnsext

DNS servers and stub commands

3F /aml_s905_uboot

U-boot DDR模组~

mizztgc /konaste-linux

Unofficial script for playing KONAMI Amusement Game Station (Konaste/コナステ) games on Linux, using Wine

ubihazard /ddr5-spd-recovery

DDR5 SPD EEPROM恢复工具。

Liu-Cheng /cycle-accurate-SystemC-simulator-over-ramulator

An example of using Ramulator as memory model in a cycle-accurate SystemC Design

Elphel /eddr3

https://git.elphel.com/Elphel/eddr3 之镜

d953i /Custom_Part_Data_Files

Xilinx PCIe to MIG DDR4 example designs and custom part data files

hellojavaer /ddal

DDAL(Distributed Data Access Layer) is a simple solution to access database shard.

JacobMcSeveney /ddr-resocket-multichannel-dma

Open-source multi-channel DDR DMA controller for FPGA: 4 write channels, 5 read channels, async FIFOs, address generation, and arbitration.

limyz /573controller

573controller allows you to transform an Arduino Leonardo or Micro into various 573 music game controllers

zslwyuan /Zynq_HLS_DDR_Dataflow_kernel_2mm

This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation

bselimoglu /SoC-ZedBoard-Zynq-7000-Labs

Hardware and Software Co-design implementations

hukenovs /adc_configurator

ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)