dram 开源项目推荐（107 个）

liquidctl /liquidctl

Cross-platform CLI and Python drivers for AIO liquid coolers and other devices

CMU-SAFARI /ramulator2

Ramulator 2.0 是一款现代化、模块化、可扩展且循环精确的 DRAM 模拟器。它支持新内存系统设计的敏捷实现和评估（例如新的DRAM标准、新兴的RowHammer缓解技术）。在我们的论文中描述 https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

PlatformLab /RAMCloud

**No Longer Maintained** Official RAMCloud repo

ModelEngine-Group /unified-cache-management

Persist and reuse KV Cache to speedup your LLM.

umd-memsys /DRAMSim2

DRAMSim2：周期精确的DRAM模拟器

CMU-SAFARI /DRAM-Bender

RAM Bender是第一个开源RAM测试基础设施，可用于轻松、全面地测试最先进的HBM 2芯片和不同形状的DDR4模块。六种原型可在不同的DSP板上提供。在我们的预印本中描述：https://arxiv.org/pdf/2211.05838.pdf

mjlaine /mcmcstat

MCMC toolbox for Matlab

hdl-util /sdram-controller

通用FPGA SDRAM控制器，最初为AS4C4M16SA设计

comsec-group /phoenix

“Phoenix：带有自我纠正同步的DDR5的Rowhammer攻击”（IEEE S&P '26）的伪影

Paradoxdov /memforge

UEFI内存诊断工具——14项压力测试，每芯片卡位映射，MCA捕获，马拉松模式，含DIMM保修信息的明文判决

tukl-msd /DRAMSpec

A High-Level DRAM Timing, Power and Area Exploration Tool

blark /a500plus-chipram-expansion

A 1MB chip RAM expansion for the A500+

iisys-sns /FlippyRAM

FlippyRAM is an automated framework for testing and analyzing Rowhammer vulnerabilities in DRAM. It combines rowhammer tools and supports both Docker and ISO-based execution, making it a powerful resource for hardware security research.

llopis /dram-tester

Sample Arduino program to test 4164 DRAM chips.

harvard-acc /DreamRAM

DreamRAM: A Fine-Grained Configurable Design Space Modeling Tool for Custom 3D Die-Stacked DRAM

pcdeni /CaSA

Software side of an LLM running inside a DRAM chip via charge-sharing PIM (BitNet b1.58 on DRAM-Bender silicon).

CMU-SAFARI /BEER

BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.: https://arxiv.org/abs/2009.07985.

dovedevic /blimp

A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.

CMU-SAFARI /CLRDRAM

Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off": https://people.inf.ethz.ch/omu…

AnshKetchum /memorysim

An RTL-level, Chipyard-compatible DRAM simulator model for high fidelity memory simulations.