rtl-to-gds 开源项目推荐（26 个）

chipfoundry /openlane2

下一代OpenLane，从零重写，采用模块化架构

Kev1nLevin /matmul-engine

Parameterized N×N output-stationary systolic array accelerator for INT8 neural network inference. Full RTL-to-GDS flow on ASAP7 7nm using Cadence Genus + Innovus. 667 MHz, 42.7 GOPS peak throughput, 0.33 mW/GOP. SystemVerilog RTL, synthesis, place-and-route and self-checking testbench included.

Tavakalmastan /fifo-asic-physical-design

基于Cadence Innovus的FIFO ASIC物理设计|布局图→ CTS →布线→时序和功耗分析

paramsaini87 /fir-filter-gds2-flow

Complete RTL-to-GDSII flow for 32-tap FIR filter on SKY130 130nm — 33% fewer cells than OpenLane, formally verified (SAT proof), DRC/LVS clean

Mauricio-xx /eda-agents

AI/LLM-assisted circuit design using opensource tools

Mauricio-xx /chipathon-gf180mcu-librelane-examples

Chipathon GF180MCU LibreLane examples: 5 hands-on notebooks (counter bare-block, chip-top with macro, workshop slot use, multi-macro counter+ALU) for the chipathon-2026-gf180mcu-padring fork.

nivi9944 /systolic-array

8x8 INT8 systolic-array accelerator: Verilog RTL, cocotb + formal verification, RTL to GDS on Sky130 at 90.9 MHz across 9 PVT corners

Yuri-Fernando /championchip-rv32-sky130

Processador RISC-V RV32I+Zmmul multicycle do RTL ao GDSII no SkyWater SKY130 (OpenLane 2): verificação com modelo de referência, mutação 13/13, gate-level e sign-off DRC/LVS 0 · ChampionCHIP eXperience Fase 2

lowfreq-quant /openlane-lab

SkyWater SKY130 RTL-to-GDS lab with open tools (yosys/OpenROAD/Magic/KLayout/netgen), no Docker, no OpenLane

lee-cheng-han /programmable-simt-asic

Four-warp, eight-lane programmable SIMT processor with scoreboarding, divergence, banked memory, differential verification, and an ASIC RTL-to-GDS flow.

Raushan-kumar0 /riscv-rtl2gds-sky130

RV32I core taken from RTL to GDSII in SkyWater 130nm with LibreLane: DRC/LVS clean, 0.24 mm², with topics asic, physical-design, openroad, sky130, riscv.

Manas-Punjabi /rv32i-soc-asic

5-stage RV32I SoC with a matrix-multiply accelerator, APB peripherals and SRAM macros, taken from RTL to a DRC- and LVS-clean layout on SkyWater 130 nm with OpenROAD.

ansh07verma /SiliconNPU

RTL-to-GDS physical design of a parameterized MAC accelerator using open-source ASIC tools (Yosys, OpenLane, Sky130)

karder1 /openroad-alu-rtl-to-gds

8-bit ALU RTL-to-GDSII physical design using OpenROAD-flow-scripts and Nangate45.

AlexOnTheStorm /systolic-array-rtl2gds

Open-source RTL-to-GDS of a 4x4 INT8 systolic array on SKY130 with LibreLane: DRC/LVS-clean GDS, per-corner timing, honest limits. Not a tape-out.

Manas-Punjabi /matmul-accel-asic

Parameterized matrix-multiply accelerator in SystemVerilog, taken from RTL to a DRC- and LVS-clean layout on SkyWater 130 nm with OpenROAD.

Shreyasimum /custom-full-adder-rtl2gds

End-to-end Digital VLSI project demonstrating a Full Adder from RTL to GDS using Yosys and OpenROAD, extended with a custom CMOS Full Adder standard cell and system-level evaluation.

AnonymousCandela /registre-ar-asic-65nm

Registre d'adresse multifonction 4 bits : flot ASIC complet RTL → layout en TSMC 65 nm (VHDL, Cadence Genus, Innovus, NCSim)

vikyathhj-ui /prefix-adder-alu-sky130

该项目在 GitHub 上没有填写描述

mikelix /gstack-tutorial-2

Build an open-source AI-agent end-to-end EDA system on WorkBuddy: RTL-to-GDS on SkyWater SKY130, four-gate verification chain, byte-reproducible GDS, driven by gstack plus two domain AI agents. Bilingual (EN/ZH).