cadence-innovus 开源项目推荐（18 个）

ArjunPShetty /32-bit_RISC-V_Processer_for_HPC

RISC-V RV32I 5-Stage Pipelined Processor

Tavakalmastan /fifo-asic-physical-design

基于Cadence Innovus的FIFO ASIC物理设计|布局图→ CTS →布线→时序和功耗分析

pocper /IC_Contest

全國大學校院積體電路設計競賽 實作練習

Ad1thh /Final-Project-EV

Fault-tolerant RV32E RISC-V core in SystemVerilog. Features TMR PC/ALUs, DMR fail-safe control unit, and SEC-DED ECC regfile. Complete RTL-to-GDSII ASIC implementation in Cadence Genus & Innovus on 90nm standard cells @ 100 MHz (0.0 ps slack, 0 DRC/LVS violations, GDSII layout verified).

SilviaB24 /DLX-Processor-Portfolio

Full RTL-to-GDSII implementation of a 32-bit RISC Processor. Features Physical Design (P&R), CTS, and Timing Closure using Synopsys DC & Cadence Innovus.

SUJITH-PEDAPATI /FPGA_BASED_CNN_ACCELARATOR

Hardware implementation of a CNN accelerator for handwritten digit recognition using Verilog RTL, FPGA deployment on Zynq-7000, and ASIC synthesis and physical-design exploration with Cadence Genus and Innovus.

srisaikrishnapavan /motorcontrol_soc

The development of SOC for BLDC motor control (designed from RTL to GDSII)

PreethamSK163 /Publication-1-Dynamic-Reconfigurable-Binary-Multiplier-Patent

Dynamic reconfigurable binary multiplier using quadrant decomposition and adaptive row bypassing for scalable, low-power operation. Designed in Verilog and implemented on TSMC 180nm/90nm using Cadence tools. Published Indian patent (202541080342).

SeanS4 /riscv-asic-physical-design

32-bit RISC-V ASIC physical design featuring a custom standard cell library, bit-sliced datapath routed in Cadence Virtuoso, and automated Cadence Innovus implementation.

ShahabuddinDanish /riscv-lite-processor

5-stage pipelined RISC-V (RV32I subset) processor in SystemVerilog that runs compiled C through variable-latency memories over an OBI-style request/ready protocol. Full ASIC flow: Synopsys DC synthesis at 641 MHz and Cadence Innovus place & route on NanGate 45 nm, plus OpenRAM SSRAM integration.

PreethamSK163 /Publication-3-Adaptive-Quadrant-Multiplier-SCI-Journal

Adaptive Quadrant (AQ) reconfigurable 16-bit multiplier using quadrant decomposition and row bypassing for low-power operation. Implemented in RCA and hybrid prefix adder variants across TSMC 180nm/90nm using Cadence tools. Achieves significant power and area reduction with scalable architecture. SCI journal manuscript under review.

Humbert416 /eda-script-copilot

LLM-powered CLI that generates Cadence Innovus TCL scripts from natural-language IC design tasks. Built on the Anthropic API with retrieval over EDA documentation.

ShahabuddinDanish /iir-filter-vlsi

Full VLSI design flow for a 1st-order IIR low-pass filter. It includes VHDL RTL, fixed-point C model, Synopsys DC synthesis with clock gating, and Cadence Innovus place & route. The advanced architecture of the filter applies J-look-ahead, pipelining, and retiming to achieve 581 MHz, a 47% throughput gain over the standard architecture.

MainakSil /MainakSil

Config files for my GitHub profile.

PreethamSK163 /Publication-2-Softmax-Processing-Unit-Patent

Low-power fixed-point Softmax processing unit with LUT-based exponentiation and an 8-stage pipelined Mitchell logarithmic divider. Designed in Verilog and implemented on TSMC 180nm using Cadence tools. Achieves 1 output/cycle throughput and 8.9× speedup over sequential division. Patent under review.

Hadleeraj /MSDAP-ASAP7-ASIC

Mini Stereo Digital Audio Processor taken RTL-to-GDSII on ASAP7 7 nm: stereo Verilog RTL, SRAM integration, Genus synthesis, Innovus implementation, and verification docs.

JustinFCalderon /chip-stitch-boundary-search

Method study of a VLSI chip-stitch boundary search (UCLA ECE 201A): enumerates its cost and subset coverage, and shows the objective prefers a layer subset the search structurally cannot reach. Python stdlib only, no EDA tools.

MainakSil /DES-ASIC-RTL-to-GDSII

Complete ASIC implementation of the OpenCores DES core using Cadence Genus, Innovus, and Synopsys PrimeTime, from RTL synthesis to GDSII.