constrained-random 开源项目推荐（23 个）

OSVVM /OSVVM

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

fvutils /pyvsc

Python packages providing a library for Verification Stimulus and Coverage

agra-uni-bremen /crave

Constrained random stimuli generation for C++ and SystemC

imaginationtech /constrainedrandom

A Python package for creating and solving constrained randomization problems.

gopro-uvm-rtl-verification /RISC-V-CPU-Core-UVM-Based-ISA-Compliance-Verification

RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

abdo-ehab-euv /sram-controller-uvm-verification

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

Tharunreddym /riscv-pipeline-verification

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

Hampton-bit /uvm-yapp-router-verification-yapp-uvc

UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)

Tharunreddym /sram-uvm-verification

SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

Tharunreddym /axi4-verification

AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

AryaD-ece /systemverilog-valid-ready-pipeline

Backpressure-safe 1-stage valid-ready pipeline in SystemVerilog with constrained-random verification, assertions (SVA), and waveform validation.

akramkhan292 /memory-verification-env

SystemVerilog memory verification using constrained-random stimulus, mailboxes, monitors, and a reference checker.

Nam24-dot /apb4-axi4-uvm-verification-portfolio

Public portfolio of APB4 and AXI4 verification methodology using SystemVerilog, UVM, SVA and coverage.

k-pitaliya /FSM-Digital-Controller

Multi-state Mealy/Moore FSM in SystemVerilog with SVA assertions, constrained-random testbenches, and functional coverage — synthesizable on Xilinx FPGAs

Ezed9 /async-fifo-verif

Dual-clock asynchronous FIFO in SystemVerilog with layered verification: constrained-random testbench, functional coverage, SVA, SymbiYosys formal spec

akramkhan292 /FIFO_DESIGN-VERIF

Learning project: parameterized FIFO RTL with an evolving SystemVerilog/UVM verification environment.

alwilson /smt2_rand_sampler

Explorations in Uniform Sampling of SMT2 Constraints

satchmakua /manifold-cov

Constrained-random verification and functional coverage for AI agents, with seeded bug reproduction

GHOSTALERT /alu-verification-sv

BEVD205L: verification of a 4-bit ALU with a constrained-random, self-checking SystemVerilog testbench (ModelSim, TCL automation, coverage, Perl regression summary)

aatifjunaid /Constrained-Random-Verification-of-a-Synchronous-FIFO

Constrained-random SystemVerilog verification of a synchronous FIFO with a scoreboard, SVA, functional coverage and 10 injected-bug mutation testing.