openrisc 开源项目推荐（28 个）

larsbrinkhoff /awesome-cpus

所有中央处理器和MCU文档集中在一个地方

s-macke /jor1k

Online OR1K Emulator running Linux

openrisc /mor1kx

mor1kx - an OpenRISC 1000 processor IP core

optimsoc /optimsoc

OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores

gabriele-galeotti /SweetAda

Ada-language framework

kuopinghsu /callgraph-gen

Generating the call graph from elf binary file

PacoReinaCampo /MPSoC-DV

Multi-Processor System on Chip verified with UVM/OSVVM/FV

PacoReinaCampo /SoC-DV

System on Chip verified with UVM/OSVVM/FV

bandvig /or1k_marocchino

OpenRISC processor IP core based on Tomasulo algorithm

janweinstock /or1kiss

An OpenRISC 1000 Instruction Set Simulator

ilyakurdyukov /ida-openrisc

OpenRISC 1000 processor module for IDA 7.x

PacoReinaCampo /PU-DV

Processing Unit verified with UVM/OSVVM/FV

andrakis /Elispidae

Lisp-based stackless interpreter and platform, including microthreading. Features taken from Lisp and Erlang.

4rchura /awesome-cpu-design

A curated awesome list of royalty-free, open-source CPU design and architecture resources (RISC-V, OpenRISC).

snps-virtualprototyping /ocx-or1kiss

OpenCpuX wrapper for the or1kiss OpenRISC ISS

timvideos /qemu-litex

该项目在 GitHub 上没有填写描述

PacoReinaCampo /MPSoC-OR1K

Multi-Processor System on Chip with OpenRISC-32 / OpenRISC-64

PacoReinaCampo /PU-OR1K

Processing Unit with OpenRISC-32 / OpenRISC-64

tiwut /OpenRISC-64

A custom 64-bit single-core RISC-V processor designed from scratch in SystemVerilog. Built with a modular architecture intended to serve as a building block for future multi-core scaling.

azbezd /charmera-sboy

Read, inspect and patch one Buildwin camera variant: USB backups, ST7735 support and artistic image effects.