processor-design 开源项目推荐（168 个）

katef /eurorack-cpu

A CPU implemented in a modular synthesizer

tscheipel /HaDes-V

HaDes-V 是用于学习微控制器设计的开放教育资源。它引导你使用 SystemVerilog 和 FPGA 工具创建流水线式 32 位 RISC-V 处理器。该资源由 TU Graz 的 EAS Group 开发，将硬件/软件协同设计中的动手练习与在 Basys3 FPGA 板上的实际实现相结合。

zslwyuan /Basic-SIMD-Processor-Verilog-Tutorial

Verilog 中实现了一个简单的 SIMD 处理器，核心是一个 16 位的 SIMD 算术逻辑单元。2 的补算计算在本算术逻辑单元中实现。算术逻辑单元操作将耗时两个时钟。第一个时钟周期用于将值加载到寄存器中。第二个周期用于执行操作。6 位操作码用于选择函数。指令码（包括操作码）将为 18 位。

peilin-chen /Zhulong-RISCV-CPU

CPU Design Based on RISCV ISA

RISC-KC /basic_rv32s

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

shehanmunasinghe /tinyGPU

tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

mpskex /chisel-npu

Chisel implementation of Neural Processing Unit for System on the Chip

aofarmakis /Nibbling-bits

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

alirezakay /RISC-CPU

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Amey-Thakur /COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB

CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] | SE Semester IV | Computer Engineering

darklife /udarkrisc

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

Awais-Asghar /Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).

KevinWang96 /Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip

EE577b-Course-Project

sixblade325 /WaterHand-Processor-Development-Skills

Codex skills for Chisel/RISC-V processor development: microarchitecture, RTL verification, Vivado timing analysis, and FPGA optimization.

qossayrida /PipelineProcessorDesign

Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.

AnkurRyder /8085-Processor

8-bit RISC Processor on Logisim

Sarst04 /SARV

SARV A Risc-V

HafizMutahirAhmed /RV32I-5-Stage-Processor

A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.

Zaneham /voyager-fds

The Voyager flight computer on SKY130 silicon. 58 cells. Currently 24 billion km away.

rj45 /nanogo

NanoGo a Go (golang) Subset for Homebrew / Hobby CPUs