Verilog-Design-Examples

Verilog 设计示例，带有自检测试平台。半叠加器、全加法器、多路复用器、算术逻辑单元、D触发器、使用Mealy机和Moore机的序列检测器、1的数量、二进制转灰制转换、上下计数器、时钟分频器、PIPO、n位通用移位寄存器、4位LFSR、单端口RAM、双端口RAM、同步先进先出、异步先进先出、8x8顺序乘法器

  • 语言Verilog
  • 默认分支main
  • 大小129 KB
  • 更新2024年1月29日
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Verilog-Design-Examples

  • Use Verilog/System Verilog for design
  • Always write a Testbench for a design
  • Testbench should be self-checking test bench
  • Testbench should use task for sending input data to the DUT

Verilog Designs with Testbenches

  1. Half Adder
  2. 1-bit Full Adder
  3. 1-bit Full Adder using Half Adder
  4. 4-bit full adder using Half Adder
  5. Mux using Case statement
  6. Mux using with the use logical expression
  7. Mux using Conditional operator
  8. ALU
  9. D Flip Flop with synchronous reset
  10. D Flip Flop with asynchronous reset
  11. Sequence Detector using Mealy machine (1101, Non-Overlapping)
  12. Sequence Detector using Moore machine (1101, Non-Overlapping)
  13. Sequence Detector using Mealy machine (1101, Overlapping)
  14. Sequence Detector using Moore machine (1101, Overlapping)
  15. Count the Number of 1s
  16. Binary to Gray Conversion
  17. Up Down Counter
  18. Random Counter
  19. Clock Divider
  20. PIPO
  21. n bit universal shift register
  22. 4 bit LFSR
  23. Custom Design
  24. Single port RAM (128x8)
  25. Dual port RAM (128x8)
  26. Synchronous FIFO
  27. Asynchronous FIFO
  28. 8x8 Sequential Multiplier
  29. 64 bit Pipelined Multiplier

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