verilog-a 开源项目推荐（31 个）

pascalkuthe /OpenVAF

创新的Verilog-A编译器

RarityBrown /ic-self-learning

微电子和集成电路自学指南

dwarning /VA-Models

Verilog-A simulation models

ColsonZhang /VerilogA-Wave-Generator

这些代码用于生成VerilogA代码，可直接用于幽灵仿真。生成的VerilogA代码的功能是根据你的设置生成特定的波形。设置是在 Python 代码（main.py）中完成的，这将大大简化编码工作。

ACMmodel /ACM-MOSFET-models

A simple MOSFET model for analog/RF IC design and simulation

JaimeHW /RSpice

Modern Analog and Mixed-Signal Electronic Circuit Simulator that runs on on the desktop and in the browser

keikawa /Verilog-A-photonic-model-library

Verilog-A model library for photonic devices and components used in electronics-photonics co-simulation

ncas-tum /heracles

HfO2 Ferroelectric Capacitor VerilogA Compact Model for Circuit Simulation

akashlevy /WP-RRAM-SPICE-Model

A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley

akashlevy /pyxbar

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

RarityBrown /blog

Some ramblings about my major. 一些有关我的专业的碎碎念

thennen /Synaptogen

A fast generative model for stochastic memory cells

ShabbyGayBar /verilogaLib

Library of Verilog-A models

pouryahoseini /Genetic-Algorithm-Processor

A digital genetic algorithm processor

rpm2003rpm /vagen

Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)

nikacvet /vscode-verilogA

Language support in Visual Studio Code for Verilog-A

gnucap /gnucap-adms

defunct. use repo on savannah

joaln27 /devphys

Open-source TCAD for SkyWater Sky130 calibrated against measured silicon from 300 K to 77 K - drift-diffusion, dopant freeze-out, cryogenic SS saturation quantified, OpenVAF/ngspice compact-model loop

pyadms /pyadms

Python Automatic Device Model Synthesizer

das-dias /morphnet

A bidirectional netlist parser built on Lark, enabling translation between SPICE-family circuit netlist formats (HSPICE, Xyce, Spectre, Spectre-SPICE) and Verilog-AMS.