veriloga 开源项目推荐（12 个）

RarityBrown /ic-self-learning

微电子和集成电路自学指南

muhammadaldacher /Analog-Design-of-1.9-GHz-PLL-system

This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.

ColsonZhang /VerilogA-Wave-Generator

这些代码用于生成VerilogA代码，可直接用于幽灵仿真。生成的VerilogA代码的功能是根据你的设置生成特定的波形。设置是在 Python 代码（main.py）中完成的，这将大大简化编码工作。

muhammadaldacher /Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC

This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.

boltma /Scalable-FeFET

A scalable FeFET compact model

muhammadaldacher /Modeling-of-4-bit-Flash-ADC-and-4-bit-DAC

This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.

akashlevy /WP-RRAM-SPICE-Model

A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley

RarityBrown /blog

Some ramblings about my major. 一些有关我的专业的碎碎念

Joschua-Conrad /Transient-Simulation-of-Dynamic-Comparator-Noise

Verilog-A test block for estimating noise and offset of a dynamic comparator in a transient simulation. Uses the Confidence-Boosting concept published at NEWCAS 2024.

rpm2003rpm /vagen

Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)

nikacvet /vscode-verilogA

Language support in Visual Studio Code for Verilog-A

RarityBrown /verilog-a

My Verilog-A module for simulation