system-on-chip-design 开源项目推荐（16 个）

arm-education /Introduction-to-SoC-Design-Education-Kit

Education kit for teaching introductory Arm-based system-on-chip design on FPGA with lectures and practical labs (educational)

aesc-silicon /ElemRV

ElemRV - 端到端开源 RISC-V 微控制器

arm-education /Advanced-System-on-Chip-Design-Education-Kit

Education kit for teaching advanced Arm Cortex-A system-on-chip design on FPGA platforms with lectures and hands-on labs (educational)

arm-education /Modern-System-on-Chip-Design-on-Arm

高级学生和工程师使用Arm Cortex-A现代SoC设计教材：架构、互连、验证与制造（教育用）

arm-education /System-on-Chip-Design-with-Arm-Cortex-M-Processors

Reference book for SoC and FPGA designers integrating Arm Cortex-M processors with AMBA bus architectures (educational)

ShekharShwetank /RISC-V_RTL2GDSII

学习路径：RISC-V 片上系统（SoC）设计，从寄存器传输级别（RTL）到 GDSII 布局 |使用开源EDA工具完成完整的VLSI设计流程。

wyvernSemi /Articles

收集的 PDF 文章文档，涵盖协同仿真、嵌入式系统、软件开发以及逻辑设计与验证等主题

MohamedHussein27 /SoC-Design-Connecting-RISC-V-Processor-with-Multiple-peripherals-using-APB-Bus

This project showcases a Verilog implementation of an System on Chip design where the RISC-V processor is connected to multiple peripherals using APB bus

dngvmnh /Cryptography

This project focuses on the design and implementation of a digital security system incorporating cryptographic algorithms like Caesar, ChaCha, AES, and Prince, alongside the development of electronic circuits targeting preconfigured microcontrollers within limited hardware environments.

OmarAskour /SOC-s

Projects System On Chip (Zynq700)

itworks99 /vtx1

Balanced ternary logic SoC with CPU, memory controllers, and complete synthesis flow for silicon fabrication

JeromeStephenson /genesis-rv32-soc

genesis-RV32-SoC is a custom, from-scratch 32-bit RISC-V (RV32I) System-on-Chip in SystemVerilog. It features a 5-stage pipelined CPU, FreeRTOS boot support, and SiFive-compatible peripherals (CLINT, PLIC, UART, GPIO).

priyanka-p01 /SoC-with-VerilogHDL-and-Verilog-conceptsheet

Documented my learnings of the System-on-Chip course using Verilog. Verilog enthusiasts interested in adding more VHDL concepts into this repository are more than welcome to fork, clone and add contributions!

ShekharShwetank /RISC-V_Reference_SoC_Tapeout_Program_Phase_2

RISC-V Reference SoC Design and Tapeout Program Phase 2 personal documentation

S-Steven-Joshua /JS-SoC

32-bit single-cycle RISC-V SoC in SystemVerilog featuring an APB interconnect, UART, PWM, Timer and I2C peripherals, and a Java-based control-word generator for memory-mapped peripheral configuration.

AlexanderGSC /Mini-Soc-Acc

Development of a minimal RISC-V System on Chip and integration with a computational accelerator written in Verilog. It serves as an example of a minimal architecture and as a foundation for future expansions (real hardware accelerators for scientific computing and AI).