risc-cpu 开源项目推荐（13 个）

ZipCPU /zipcpu

一个体积小、重量轻的RJ中央处理器软核

lxp32 /lxp32-cpu

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

uttamsaha /14-bit-RISC-CPU-Implementation

14-bit CPU implementation in Logisim. This is a 14-bit RISC CPU logisim implementation. All files are included in this single repository.

MALEKDE /SystemVerilog-RTL-Design

A collection of digital hardware components designed in SystemVerilog, including counters, registers, an 8-bit ALU, and a 4×8 register file. Built to explore RTL design, digital logic, and verification while progressing toward a simple RISC CPU implementation.

BrosnanYuen /MIPS_Processor

16-bit MIPS Processor from scratch in VHDL

Howeng98 /RISC-V-CPU

risc-v-cpu

MALEKDE /8-BIT-ALU-LookUp-Table-Logisim

8-bit ALU lookup-table project for Logisim-evolution

EmbeddedCamerata /Simple-RISC-CPU

Simple RISC CPU. 根据夏宇闻《Verilog数字系统设计教程》第2版17.1节简化RISC_CPU设计修改

LocLam134 /4-Bit-CPU_Datapath

4-Bit RISC CPU Datapath with 3-Stage Pipeline implemented in Verilog HDL & verified on Xilinx Virtex-7 (88/88 checks passed).

FREEWING-JP /zpu

The Zylin ZPU

SaheelFaisal /verilog-pipelined-risc-cpu

Structural Verilog implementation of a pipelined RISC CPU datapath and control unit based on Mano & Kime.

kianmajl /A2K-CPU

A 32-bit single cycle RISC CPU based on Harvard architecture with no cache or pipeline, by having very simple and reduced instruction set it can be used for educational purpose.

bryanherdianto /8bit-processor-core

Synthesizable 8-bit RISC-style processor core in VHDL with 16-bit instructions, a 16x8-bit register file, 8-state FSM, and ModelSim tests.