netlist 开源项目推荐（117 个）

emsec /hal

HAL – The Hardware Analyzer

nturley /netlistsvg

draws an SVG schematic from a JSON netlist

google /pcbdl

PCB Design Language: A programming way to design schematics.

keplertech /naja

Open-source EDA framework for RTL elaboration, netlist analysis, and transformation, with C++ and Python APIs

circuitgraph /circuitgraph

在 Python 中将电路作为图处理的工具

byuccl /spydrnet

一个用于分析和转换DSP网表的灵活框架。官方资料库。

aaanthonyyy /CircuitNet

A hand-drawn schematic sketch recognizer and converter. Three-Step pipeline: Component detection using traditional image processing; Component classification using a custom trained CNN; Schematic generation using a proprietary generation algorithm.

IntelligentElectron /universal-netlist

Give AI agents the power to read Cadence, Altium, and KiCad designs

electron-lang /electron

A mixed signal netlist language (pre-alpha)

keplertech /naja-verilog

A standalone structural (gate-level) verilog parser

pablov55 /Beginner-s-Guide-to-KiCad

本指南将教你从原理图构建到 PCB 设计的 KiCad 全部基础知识。还会教你如何添加库、创建自己的符号和封装、导出钻孔和 Gerber 文件，以及更多帮助你开启 KiCad 之旅的提示！

SpiceSharp /SpiceSharpParser

SPICE netlists parser for .NET

jimwang99 /parser-for-chip-design

A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).

arasgungore /netlist-solver

A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.

BUAA-CLab /CircuitMind

The code about TC-Bench and CircuitMind

openecos-projects /ecc-tools

一个开源的EDA基础设施及从网表到GDS用于ASIC设计的工具。

byuccl /spydrnet-tmr

SpyDrNet项目的TLR实用程序

ganeshgore /spydrnet-physical

这是一个用于物理设计相关转换的SpyDrNet插件

kailiuXD /xdcom

This is a demo for still image compression application

akashlevy /pyxbar

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations